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    SCHEMATIC DIAGRAM NAND GATES Search Results

    SCHEMATIC DIAGRAM NAND GATES Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    BLM15PX330BH1D
    Murata Manufacturing Co Ltd FB SMD 0402inch 33ohm POWRTRN PDF
    BLM15PX600SH1D
    Murata Manufacturing Co Ltd FB SMD 0402inch 60ohm POWRTRN PDF
    MGN1D120603MC-R7
    Murata Manufacturing Co Ltd DC-DC 1W SM 12-6/-3V GAN PDF
    LQW18CN4N9D0HD
    Murata Manufacturing Co Ltd Fixed IND 4.9nH 2600mA POWRTRN PDF
    LQW18CNR33J0HD
    Murata Manufacturing Co Ltd Fixed IND 330nH 630mA POWRTRN PDF

    SCHEMATIC DIAGRAM NAND GATES Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    74169 SYNCHRONOUS 4-BIT BINARY COUNTER

    Abstract: 74139 demultiplexer 3-8 decoder 74138 pin diagram 3-8 decoder 74138 CI 74151 pin diagram 41 multiplexer 74153 JK Shift Register 74195 bcd counter using j-k flip flop diagram Multiplexer 74153 CI 74138
    Contextual Info: AUGUST 1984 semiconductor MSM60300, MSM60700, MSM61000 CMOS GATE ARRAYS GENERAL DESCRIPTION FEATURES The OKI MSM60300, MSM60700, and MSM61000 gate arrays are fabricated using state-of-the-art 3/i dual-layer metal silicon gate CMOS technology. A unit cell consists of 4 pairs o f transistors


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    MSM60300, MSM60700, MSM61000 MSM61000 74169 SYNCHRONOUS 4-BIT BINARY COUNTER 74139 demultiplexer 3-8 decoder 74138 pin diagram 3-8 decoder 74138 CI 74151 pin diagram 41 multiplexer 74153 JK Shift Register 74195 bcd counter using j-k flip flop diagram Multiplexer 74153 CI 74138 PDF

    M74LS132P

    Abstract: M74LS19P M74LS24P
    Contextual Info: MITSUBISHI LSTTLs M 74LS24P QUADRUPLE 2-IN P U T POSITIVE NAND SCHMITT TRIGGER DESCRIPTION T h e M 7 4 L S 2 4 P is a s e m ico n d u c to r in teg rated c irc u it c o n ­ ta in in g fo u r 2 -in p u t po sitive-logic N A N D gates having a s c h m itt trigg er fu n c tio n and negative-logic N O R gates.


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    M74LS24P b2LHfl27 0013Sbl M74LS132P M74LS19P M74LS24P PDF

    Contextual Info: , -.r-' _ b3E • rn r - „ T T i M IT S U B IS H I BIPO LAR D IG IT A L ICs ^ 2 4 ^ 0 2 7 OGlil?'! STb ■ M I T 3 MITSUBISHI _ _ M54605P iw.w-.-www. DGTL LOGIC DUAL P E R IP H E R A L P O S IT IV E NAND D R IVER DESCRIPTION M 54605P is a semiconductor integrated circuit containing 2


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    M54605P 54605P PDF

    htri

    Abstract: SLA6028 SLA6190 SLA6040 CL 6017 SLA6083 SLA6123 SLA6158 SLA6009 SLA6059
    Contextual Info: DATA SHEET PRELIMINARY ASIC SLA60000 Series May 2000 SLA60000 SERIES HIGH DENSITY GATE ARRAY § DESCRIPTION The EEA SLA60000 Series is a family of ultra high-speed VLSI CMOS gate arrays utilizing a 0.25µm “sea-of-gates” architecture. • • • Ultra-high-speed, high density and low power consumption


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    SLA60000 107ps htri SLA6028 SLA6190 SLA6040 CL 6017 SLA6083 SLA6123 SLA6158 SLA6009 SLA6059 PDF

    74hc395

    Abstract: spice model 74hc14 74HC00 pspice model library atmel U136 7400 nand gate LS7400 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR ABEL Design Manual MARKING CODE reran plus generators design with 74ls00
    Contextual Info: Table of Contents Synario ECS and Board Entry Product Overviews Manual You are here Programmable IC Entry Manual Synario ECS and Board Entry Manual ABEL Design Manual Schematic and Board Tools Manual March 1997 Synario ECS and Board Entry Manual 1 Table of Contents


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    PDF

    EVQ-WKA001

    Abstract: ST MICRO M58WR032KB70ZB6EF SST 25WF040 MT48H32M16-75 HX1188 Rotary Encoder Interface ADP1710,TSOT5 ADP2291 usb to rj45 extenders SJ27
    Contextual Info: ADSP-BF526 EZ-Board Evaluation System Manual TM Revision 1.0, August 2008 Part Number 82-000212-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information 2008 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent


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    ADSP-BF526 Device-22, EVQ-WKA001 ST MICRO M58WR032KB70ZB6EF SST 25WF040 MT48H32M16-75 HX1188 Rotary Encoder Interface ADP1710,TSOT5 ADP2291 usb to rj45 extenders SJ27 PDF

    TC5816AFT

    Abstract: tc5816ft TC5816 toshiba NAND ID code TSOP44-P-400B nv16 NAND memory nand toshiba reference
    Contextual Info: TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT TC5816AFT PRELIMINARY 16Mbit 2M x 8 BIT CMOS NAND EEPROM Description The TC5816 is a 5 volt 16M bit NAND Electrically Erasable and Programmable Read Only Memory (NAND EEPROM) with a spare 64k x 8 bits. This device is organized as 264 bytes x 16 pages x 512 blocks. The device has a 264 byte static register which allows


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    TC5816AFT 16Mbit TC5816 NV16010196 TSOP44-P-400B TC5816AFT tc5816ft toshiba NAND ID code TSOP44-P-400B nv16 NAND memory nand toshiba reference PDF

    tc58v32ft

    Abstract: TC58V32
    Contextual Info: IN TEG RA TED CIRCUIT TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT TC58V32 FT TO SHIBA TECHNICAL DATA SILICON GATE CMOS 32 MBIT 4 M X 8 BITS CMOS NAND E2PROM TENTATIVE DATA DESCRIPTION The TC58V32FT device is a single 3.3-volt 33 M (34,603,008) bit NAND Electrically Erasable and


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    TC58V32 TC58V32FT 528-byte, 528-byte TC58V32FT-- PDF

    Contextual Info: SN55461 THRU SN55463 SN75461 THRU SN75463 DUAL PERIPHERAL DRIVERS ą SLRS022A − DECEMBER 1976 − REVISED OCTOBER 1995 PERIPHERAL DRIVERS FOR HIGH-VOLTAGE, HIGH-CURRENT DRIVER APPLICATIONS • • • • 1A 1B 1Y GND LOGIC SN55461 AND FK, JG SN55462 NAND


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    SLRS022A SN55461 SN55463 SN75461 SN75463 SN55461, SN55462, SN55463 SN75461, SN75462, PDF

    msl 9350

    Abstract: TTL SN7400N SN7400N SN7400P 7400 functional cross-reference TEXAS INSTRUMENTS SN7400N ttl nand gate 7400 quad
    Contextual Info: SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003 D Package Options Include Plastic Small-Outline D, NS, PS , Shrink Small-Outline (DB), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and


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    SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 SDLS025B SN5400 SN54S00 msl 9350 TTL SN7400N SN7400N SN7400P 7400 functional cross-reference TEXAS INSTRUMENTS SN7400N ttl nand gate 7400 quad PDF

    SN75450

    Abstract: sn75450a SN55451B SN55452B SN55453B SN55454B SN75451B SN75452B SN75453B SN75454B
    Contextual Info: SN55451B, SN55452B, SN55453B, SN55454B SN75451B, SN75452B, SN75453B, SN75454B DUAL PERIPHERAL DRIVERS SLRS021B – DECEMBER 1976 – REVISED SEPTEMBER 1999 D D D D D D D D D Characterized for Use to 300 mA High-Voltage Outputs No Output Latch-Up at 20 V After


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    SN55451B, SN55452B, SN55453B, SN55454B SN75451B, SN75452B, SN75453B, SN75454B SLRS021B 300-mil SN75450 sn75450a SN55451B SN55452B SN55453B SN55454B SN75451B SN75452B SN75453B SN75454B PDF

    SN75451BD

    Abstract: SN75451BP
    Contextual Info: SN55451B, SN55452B, SN55453B, SN55454B SN75451B, SN75452B, SN75453B, SN75454B DUAL PERIPHERAL DRIVERS SLRS021B – DECEMBER 1976 – REVISED SEPTEMBER 1999 D D D D D D D D D Characterized for Use to 300 mA High-Voltage Outputs No Output Latch-Up at 20 V After


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    SN55451B, SN55452B, SN55453B, SN55454B SN75451B, SN75452B, SN75453B, SN75454B SLRS021B 300-mil SN75451BD SN75451BP PDF

    Contextual Info: b3E • bE4TÖ27 GDlSlbl 3Sb « H I T S M IT S U B IS H I B IP O L A R D IG IT A L IC s M54600P MITSUBISHI DGTL LOGIC DUAL PE R IP H E R A L P O S IT IV E AND D R IVER DESCRIPTION M54600P is a semiconductor integrated circuit containing 2 PIN CONFIGURATION (TOP VIEW)


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    M54600P M54600P PDF

    TC58NVM9S3ETA00

    Abstract: TC58NVM9S3Et TC58NVM9S3E DIN2111 PA12 PA13 TC58NVM9S3
    Contextual Info: TC58NVM9S3ETA00 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 512M BIT 64M x 8 BIT CMOS NAND E PROM DESCRIPTION The TC58NVM9S3E is a single 3.3V 512Mbit (553,648,128bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 512blocks.


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    TC58NVM9S3ETA00 TC58NVM9S3E 512Mbit 128bits) 512blocks. 2112-byte 011-03-01A TC58NVM9S3ETA00 TC58NVM9S3Et DIN2111 PA12 PA13 TC58NVM9S3 PDF

    TPS2811P

    Abstract: TPS2811 TPS2811D TPS2812 TPS2812D TPS2813 TPS2813D TPS2814 TPS2815 irf840 mosfet drive circuit diagram
    Contextual Info: TPS2811, TPS2812, TPS2813, TPS2814, TPS2815 DUAL HIGHĆSPEED MOSFET DRIVERS SLVS132E – NOVEMBER 1995 – REVISED OCTOBER 2002 D Industry-Standard Driver Replacement D 25-ns Max Rise/Fall Times and 40-ns Max TPS2811, TPS2812, TPS2813 . PACKAGES TOP VIEW


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    TPS2811, TPS2812, TPS2813, TPS2814, TPS2815 SLVS132E 25-ns 40-ns TPS2811P TPS2811 TPS2811D TPS2812 TPS2812D TPS2813 TPS2813D TPS2814 TPS2815 irf840 mosfet drive circuit diagram PDF

    HP 2612 optocoupler

    Abstract: HP 2602 hp 2611 HCPL-2602 HP 2630 optocoupler HCNW137 HCNW2601 HCPL-0600 HCPL-0601 HCPL-0630
    Contextual Info: High CMR Line Receiver Optocouplers Technical Data HCPL-2602 HCPL-2612 Features Applications Description • 1000 V/µs Minimum Common Mode Rejection CMR at VCM = 50 V for HCPL-2602 and 3.5 kV/µs Minimum CMR at VCM = 300 V for HCPL-2612 • Line Termination Included –


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    HCPL-2602 HCPL-2612 MIL-STD-1772 5954-8457E 5965-3585E HP 2612 optocoupler HP 2602 hp 2611 HCPL-2602 HP 2630 optocoupler HCNW137 HCNW2601 HCPL-0600 HCPL-0601 HCPL-0630 PDF

    Contextual Info: SN55461 THRU SN55463 SN75461 THRU SN75463 DUAL PERIPHERAL DRIVERS SLRS022A - DECEMBER 1976 - REVISED OCTOBER PERIPHERAL DRIVERS FOR HIGH-VOLTAGE, HIGH-CURRENT DRIVER APPLICATIONS S N 5 5 4 6 1 , S N 5546 2, SN 55463 . . . J G P A C K A G E S N 7546 1, S N 7546 2, S N 7546 3 . . O O R P P A C K A G E


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    SN55461 SN55463 SN75461 SN75463 SLRS022A 300-mil PDF

    Contextual Info: Advance Data Sheet February 1993 £ = — AT&T Microelectronics Optimized Reconfigurable Cell Array ORCA Series Field-Programmable Gate Arrays Features • High density: 3500 to 22,000 usable gates ■ High I/O: up to 288 usable I/O ■ High performance: 80 MHz system clock rate


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    16-bit DS92-099FPGA PDF

    TC58NVG1S3CTA00

    Abstract: TC58NVG1S3C DIN2111 PA12 PA13 PA15 PA16 tc58nvg
    Contextual Info: TC58NVG1S3CTA00 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 2-GBIT 256 M x 8 BITS CMOS NAND E PROM DESCRIPTION The TC58NVG1S3C is a single 3.3 V 2-Gbit (2,214,592,512 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 2048 blocks.


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    TC58NVG1S3CTA00 TC58NVG1S3C 2112-byte TC58NVG1S3CTA00 DIN2111 PA12 PA13 PA15 PA16 tc58nvg PDF

    CB4CLED

    Abstract: vhdl code for 2-bit BCD adder CB4CLE TTL 7400 CC16CLE cb4ce code D24E XC400XL CB2CE CB16CE
    Contextual Info: Libraries Guide Xilinx Unified Libraries Selection Guide Design Elements ACC1 to BYPOSC Design Elements (CAPTURE_VIRTEX to DECODE64) Design Elements (F5MAP to FTSRLE) Design Elements (GCLK to KEEPER) Design Elements (LD to NOR16) Design Elements (OAND2 to OXOR2)


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    DECODE64) NOR16) ROM32X1) XC2064, XC3090, XC4005, XC5210, XC--90 CB4CLED vhdl code for 2-bit BCD adder CB4CLE TTL 7400 CC16CLE cb4ce code D24E XC400XL CB2CE CB16CE PDF

    xc4000 application note

    Abstract: P8202 XCS20 TQ144 XC4000 XCS05 XCS05XL XCS10 XCS10XL 188 p33 Transistor XCS20XL
    Contextual Info: Spartan and Spartan-XL Families Field Programmable Gate Arrays R DS060 v1.5 March 2, 2000 Introduction Product Specification • The Spartan series is the first high-volume production FPGA solution to deliver all the key requirements for ASIC replacement up to 40,000 gates. These requirements


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    DS060 XCS20XL-4 PQ208C 100oC) xc4000 application note P8202 XCS20 TQ144 XC4000 XCS05 XCS05XL XCS10 XCS10XL 188 p33 Transistor XCS20XL PDF

    APA600-PQ208M

    Abstract: FBGA-484 datasheet APA075 APA1000 APA150 APA300 APA450 APA750 APA150-TQ100 RPE 113
    Contextual Info: v5.8 ProASICPLUS ® Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy • • • • High Capacity Commercial and Industrial • • • I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os


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    12 volts,15 amps Regulated Power Supply Schematic Diagram

    Abstract: SMP04E
    Contextual Info: a FEATURES Four Independent Sample-and-Holds Internal Hold Capacitors High Accuracy: 12 Bit Very Low Droop Rate: 2 mV/s typ Output Buffers Stable for C L ≤ 500 pF TTL/CMOS Compatible Logic Inputs Single or Dual Supply Applications Monolithic Low Power CMOS Design


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    SMP04* SMP04 SMP04 C3131 SMP04EP SMP04EQ SMP04ES SMP04GBC 12 volts,15 amps Regulated Power Supply Schematic Diagram SMP04E PDF

    GP028

    Abstract: MB512 piix4 GP021
    Contextual Info: 82371 AB PCI-TO-ISA / IDE XCELERATOR PIIX4 — Integrated 16 x 32-bit Buffer for IDE PCI Burst Transfers — Supports Glue-less “Swap-Bay” Option with Full Electrical Isolation • Supported Kits for both Pentium'and Pentium’ ll Microprocessors — 82430TX ISA Kit


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    32-bit 82430TX 82440LX SupporA15 CLK48 GP028 MB512 piix4 GP021 PDF