SCEA003A Search Results

trung

Abstract: FB1650 GTL16612 GTL16923
Contextual Info: GTL/BTL: A LowĆSwing Solution for HighĆSpeed Digital Logic Application Report 1997 Advanced System Logic Products Printed in U.S.A. 0397–CP SCEA003A GTL/BTL: A LowĆSwing Solution for HighĆSpeed Digital Logic Application Report 1997 Advanced System Logic Products

compared CMOS TTL Logic Family Specifications

Abstract: GTL16923 trung FB1650 GTL16612
Contextual Info: GTL/BTL: A LowĆSwing Solution for HighĆSpeed Digital Logic Application Report 1997 Advanced System Logic Products Printed in U.S.A. 0397–CP SCEA003A GTL/BTL: A LowĆSwing Solution for HighĆSpeed Digital Logic Application Report 1997 Advanced System Logic Products

msi 7267 MOTHERBOARD SERVICE MANUAL

Abstract: ttl cookbook msi ms 7267 MOTHERBOARD CIRCUIT diagram "0.4mm" bga "ball collapse" height PCF 799 crystal oscillator 8MHz 4 pins smd diode MARKING F5 44C smd TRANSISTOR code marking A7 terminals diagram of smd transistor bo2 cookbook for ic 555
Contextual Info: GTL/GTLP Logic High-Performance Backplane Drivers Data Book Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information

octal tri state buffer ic

Abstract: RS flip flop IC datasheet a030101 VME64x COnnector Implementation of digital clock using flip flops quad single supply 50 Ohm Line Drivers rele smd VME64X* by vita T flip flop IC VME 160 connector
Contextual Info: T H E W O R L D L E A D E R SLL Advanced Bus Interface Logic Products Selection Guide and Reference I N D S P A N D A N A L O G SLL Advanced Bus Interface Logic Products Selection Guide and Reference Contents Page Bus Interface Solutions Overview Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Signal path designer

Contextual Info: SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349C – JUNE 2001 – REVISED NOVEMBER 2001 D D D D D D D D D D D D TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes

SN74FB2033K

Contextual Info: SN74FB2033K 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 D D D D Compatible With IEEE Std 1194.1-1991 BTL TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA BIAS VCC Pin Minimizes Signal Distortion

Signal path designer

Contextual Info: SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350C – JUNE 2001 – REVISED NOVEMBER 2001 D D D D D D D D D D D D D TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes

GTLPH1655

Abstract: SCED004 GTL1655 SN74ABT25245 SN74GTLPH1655 SN74LS00 Design Seminar Signal Transmission
Contextual Info: Application Report SCBA015A - March 2001 Fast GTLP Backplanes With the GTLPH1655 Peter Forstner and Johannes Huchzermeier Standard Linear & Logic ABSTRACT This revision of the Fast GTL Backplanes With the GTL1655 application report addresses improvements, such as the improved OEC circuitry and implementation of the

Contextual Info: SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS www.ti.com FEATURES • • • • • • • • • • Members of Texas Instruments Widebus Family UBT™ Transceivers Combine D-Type Latches and D-Type Flip-Flops for Operation in

Contextual Info: SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com SCBS481H – JUNE 1994 – REVISED APRIL 2005 FEATURES • • • • • • • • • • • • DGG OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus

datasheet a030101

Abstract: octal tri state buffer ic smd 1a5 transistor 2b7 smd 16-Pin SSOP RS-232 Transceivers CML Vt 1999 50 Ohm EIA-232 RS-423 RS-644 TLK2500
Contextual Info: T H E W O R L D L E A D E R SLL Advanced Bus Interface Logic Products Selection Guide and Reference I N D S P A N D A N A L O G SLL Advanced Bus Interface Logic Products Selection Guide and Reference Contents Page Bus Interface Solutions Overview Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

SN74GTL1655

Abstract: SN74GTLPH1655 SN74GTLPH1655DGGR Higgs 3
Contextual Info: Application Report SZZA016B - June 2001 Basic Design Considerations for Backplanes Shankar Balasubramaniam, Ramzi Ammar, Ernest Cox, Steve Blozis, and Jose M. Soltero Standard Linear & Logic ABSTRACT This application report describes design issues relevant to the parallel backplanes typically

Contextual Info: www.ti.com SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS673F – AUGUST 1996 – REVISED APRIL 2005 FEATURES • • • • • • • • • • Member of Texas Instruments Widebus Family OEC™ Circuitry Improves Signal Integrity and

Contextual Info: SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001 D D D D D Compatible With IEEE Std 1194.1-1991 BTL TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA BIAS VCC Pin Minimizes Signal Distortion

Contextual Info: SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS SCBS480K – JUNE 1994 – REVISED AUGUST 2001 D D D D D D D D D D Members of Texas Instruments’ Widebus Family UBT Transceivers Combine D-Type Latches and D-Type Flip-Flops for

Contextual Info: SN74FB2040 8-BIT TTL/BTL TRANSCEIVER SCBS173N – NOVEMBER 1991 – REVISED MARCH 2002 D D D D Compatible With IEEE Std 1194.1-1991 BTL TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA D D High-Impedance State During Power Up

Contextual Info: SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001 D D D D D Compatible With IEEE Std 1194.1-1991 BTL TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA BIAS VCC Pin Minimizes Signal Distortion

SN74FB2041A

Contextual Info: SN74FB2041A 7-BIT TTL/BTL TRANSCEIVER SCBS172M – NOVEMBER 1991 – REVISED MARCH 2002 D D D D D Compatible With IEEE Std 1194.1-1991 BTL TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA BIAS VCC Pin Minimizes Signal Distortion

Contextual Info: SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176N – NOVEMBER 1991 – REVISED JUNE 2001 D D D D D Compatible With IEEE Std 1194.1-1991 BTL TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA High-Impedance State During Power Up

SLLA067

Abstract: FB1650 FB2033A scea003a SN74FB2033K SN74FB2041A
Contextual Info: Application Report SCEA017 - April 2001 GTLP in BTL Applications Steve Blozis Standard Linear & Logic ABSTRACT This application report addresses the issues a designer might face when using a GTLP device in a BTL/FB+ application when a legacy BTL/FB+ bus implementation is still in use.

GTL1655

Abstract: SN54GTL1655 SN74ABT25245 SN74GTL1655 SN74LS00
Contextual Info: Fast GTL Backplanes With the GTL1655 Application Report 1999 Printed in U.S.A. 0299 SCBA015 Fast GTL Backplanes With the GTL1655 SCBA015 February 1999 1 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products

Contextual Info: SN74GTL2007 12ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCLS609 − MARCH 2005 D Operates as a GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing Done to JEDEC Standard

Contextual Info: www.ti.com FEATURES • • • • • • • • • • Member of the Texas Instruments Widebus Family OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference D-Type Flip-Flops With Qualified Storage Enable Translates Between GTL/GTL+ Signal Levels

Contextual Info: SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER SCES285E – OCTOBER 1999 – REVISED AUGUST 2001 D D D D D D D D D D D D DGV, DW, OR PW PACKAGE TOP VIEW OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP