SCAS339 Search Results

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCAS339H – MARCH 1994 – REVISED OCTOBER 1998 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V

lc126

Abstract: A115-A SN74LVC126A SN74LVC126AD SN74LVC126ADR SN74LVC126ARGYR LC126A
Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3ĆSTATE OUTPUTS SCAS339P − MARCH 1994 − REVISED FEBRUARY 2004 D Operates From 1.65 V to 3.6 V D Specified From −40°C to 85°C and D, DB, DGV, NS, OR PW PACKAGE TOP VIEW From −40°C to 125°C 1OE 1A 1Y

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCAS339M – MARCH 1994 – REVISED JANUARY 2003 D 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y RGY PACKAGE TOP VIEW description/ordering information This quadruple bus buffer gate is designed for

LC126A

Abstract: LVC126A A115-A SN74LVC126A SN74LVC126AD SN74LVC126ADR SN74LVC126ARGYR
Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCAS339O – MARCH 1994 – REVISED JULY 2003 D 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y RGY PACKAGE TOP VIEW description/ordering information This quadruple bus buffer gate is designed for

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCAS339Q – MARCH 1994 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y RGY PACKAGE TOP VIEW 1A 1Y 2OE 2A 2Y DESCRIPTION/ORDERING INFORMATION

lc126a

Abstract: A115-A SN74LVC126A SN74LVC126AD SN74LVC126ADR SN74LVC126ARGYR LVC126A SCAS339Q
Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCAS339Q – MARCH 1994 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y RGY PACKAGE TOP VIEW 1A 1Y 2OE 2A 2Y DESCRIPTION/ORDERING INFORMATION

lc126A

Abstract: LC126
Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCAS339Q – MARCH 1994 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y RGY PACKAGE TOP VIEW 1A 1Y 2OE 2A 2Y DESCRIPTION/ORDERING INFORMATION

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCAS339Q – MARCH 1994 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y RGY PACKAGE TOP VIEW 1A 1Y 2OE 2A 2Y DESCRIPTION/ORDERING INFORMATION

diagram Converter 24v to 12v

Abstract: SN74LVC126A SN74LVC126AD SN74LVC126ADR SN74LVC126ARGYR A115-A
Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCAS339Q – MARCH 1994 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y RGY PACKAGE TOP VIEW 1A 1Y 2OE 2A 2Y DESCRIPTION/ORDERING INFORMATION

SN74LVC126A

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCAS339D – MARCH 1994 – REVISED JANUARY 1997 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCAS339Q – MARCH 1994 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y RGY PACKAGE TOP VIEW 1A 1Y 2OE 2A 2Y DESCRIPTION/ORDERING INFORMATION

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCAS339E - MARCH I W • • • • • • • - REVISED JANUARY 1998 /" IS » D, DB, OR PW PACKAGE TOP VIEW EPIC"* (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCAS339D - MARCH 1994 - REVISED JANUARY 1997 • E P IC m E n h a nc e d- P e r f or m a nce Im pl ant ed CMOS S u b m i c r o n P r o c e s s • ESD Pr ot ec t i on E x c e ed s 2000 V Per MIL-STD-883, Me t h o d 3015; E x c e ed s 200 V

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCAS339Q – MARCH 1994 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y RGY PACKAGE TOP VIEW 1A 1Y 2OE 2A 2Y DESCRIPTION/ORDERING INFORMATION

SN74LVC126A

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCAS339H – MARCH 1994 – REVISED OCTOBER 1998 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V

Contextual Info: SN74LVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCAS339 - MARCH 1994 D, DB, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C 10E [ 1

lvc126a

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCAS339J – MARCH 1994 – REVISED MARCH 2002 D D D D D D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Inputs Accept Voltages to 5.5 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C

A115-A

Abstract: SN74LVC126A SN74LVC126AD SN74LVC126ADR SN74LVC126ARGYR
Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCAS339Q – MARCH 1994 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y RGY PACKAGE TOP VIEW 1A 1Y 2OE 2A 2Y DESCRIPTION/ORDERING INFORMATION

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCAS339Q – MARCH 1994 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y RGY PACKAGE TOP VIEW 1A 1Y 2OE 2A 2Y DESCRIPTION/ORDERING INFORMATION

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCAS339Q – MARCH 1994 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y RGY PACKAGE TOP VIEW 1A 1Y 2OE 2A 2Y DESCRIPTION/ORDERING INFORMATION

A115-A

Abstract: SN74LVC126A SN74LVC126AD SN74LVC126ADR SN74LVC126ARGYR
Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCAS339Q – MARCH 1994 – REVISED JULY 2005 FEATURES • 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y RGY PACKAGE TOP VIEW 1A 1Y 2OE 2A 2Y DESCRIPTION/ORDERING INFORMATION

SN74LVC126

Contextual Info: SN74LVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCAS339 - MARCH 1994 EPIC Enhanced-Performance Implanted CMOS Submicron Process D, DB, OR PW PACKAGE (TOP VIEW) Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C 10E [ 1

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCAS339M – MARCH 1994 – REVISED JANUARY 2003 D 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y RGY PACKAGE TOP VIEW description/ordering information This quadruple bus buffer gate is designed for

SN74LVC126A

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCAS339D - MARCH 1994 - REVISED JANUARY 1997 • • • • D, DB, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V