S-MASTER PROCESSOR Search Results

Contextual Info: SC A N S TA 101 SCANSTA101 Low Voltage IEEE 1149.1 System Test Access STA Master Te x a s In s t r u m e n t s Literature Number: SNLS057I t) a l SCANSTA101 Sem iconductor Low Voltage IEEE 1149.1 System Test Access (STA) Master General Description Features

93CS56

Abstract: doorbell ID l960 pci9080 9060ES 93C06 NM93CS06 NM93CS46 PCI9060ES doorbell
Contextual Info: PCI 9060ES T e c T T T T S T T ^ T T November 1995 VERSION 1.0 PCI Bus Master Interface Chip for Adapters and Embedded Systems Features General Description PCI Bus Master and Bus Slave transfers up to 132 megabytes/sec supporting three architectures: - PCI Direct Master adapter

Sonic DP83932

Abstract: an 9010 9010 83932 9010 plx DP83932 EISA Sonic Drive
Contextual Info: 32E D P L X TECHNOLOGY CORP b û S S m i 0000133 1 BIPLX T-52-33-55 EISA 9010 EISA Bus Master Interface Chip for National SONIC DP83932 LAN Controller Preliminary December 1990 Features_ _ EISA bus master interface for National DP83932 Ethernet Controller

Contextual Info: \y HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM IDT7007S/L Integrated Devi ce Technology, Inc. FEATURES: more using the Master/Slave select when cascading more than one device M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave Interrupt Flag

Contextual Info: HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM PRELIMINARY IDT7008S/L Integrated Device Technology, Inc. FEATURES: • • • • • more using the Master/Slave select when cascading more than one device M/S = V ih for BUSY output flag on Master, M /S = V n for BUSY input on Slave

Contextual Info: HIGH-SPEED 8 K x 16 DUAL-PORT STATIC RAM F eatures IDT7025 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device_ M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave Interrupt Flag

Shared resource arbitration

Contextual Info: miMHS PRELIMINARY March 1994 L 67005 DATA SHEET 8 KX 8 CMOS DUAL PORT RAM 3.3 VOLT FEATURES VERSATILE PIN SELECT FOR MASTER OR SLAVE: - M/S= H FOR BUSY OUTPUT FLAG ON MASTER - M/S = L FOR BUSY INPUT FLAG ON SLAVE INT FLAG FOR PORT TO PORT COMMUNICATION FULL HARDWARE SUPPORT OF SEMAPHORE

IDT70V27

Abstract: 70V27 A14L IDT70V27S cea h12
Contextual Info: HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ IDT70V27 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave

Contextual Info: HIGH-SPEED 1 6 K X 9 DUAL-PORT STATIC RAM Features * * * using the Master/Slave select when cascading more than one d e v i c e _ M/S = V ih fo r BUSY output flag on Master M/S = V il fo r BUSY input on Slave Busy and Interrupt Flag On-chip port arbitration logic

Contextual Info: HIGH-SPEED 16Kx 16 DUAL-PORT STATIC RAM IDT7026S/L Integrated D e vic e Techn olo gy, Inc. multiplexed bus compatibility IDT7026 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = H for B U S Y output flag on Master,

Contextual Info: HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM FEATURES: IDT7025S/L more using the Master/Slave select when cascading more than one device M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling

Contextual Info: HIGH-SPEED 1 6 K X 9 DUAL-PORT STATIC RAM ID T 7 0 1 6 S /L Features using the Master/Slave select when cascading more than * True Dual-Ported memory cells which allow sim ultaneous one d e v i c e _ reads of the sam e memory location M/S = V ih for B U S Y output flag on Master

A54SX72

Contextual Info: ^ c te l P r e lim in a r y v1„0 CorePCI Target+DMA Master 33/66MHz P ro d u ct S um m ary Section In te n d e d U s e • High-Performance 33MHz or 66MHz PCI Target+DMA Master Applications Page I/O Signal Descriptions 415 Supported Comm ands 418 Device Utilization

PB256C

Abstract: vhdl code for flip-flop PB256 PCI32 PQ208 QL5032 QL5032-33 "ESP"
Contextual Info: QL5032-33 - QuickPCI ESP 33 MHz/32-bit PCI Controller with Embedded Programmable Logic and Dual Port SRAM Updated: 29-Apr-99 DEVICE HIGHLIGHTS High Performance PCI Controller - 32-bit / 33 MHz Master/Target PCI Controller Zero-wait state PCI Master provides 132 MB/s transfer rates

QL5032

Abstract: 64x18 synchronous sram pci verilog code
Contextual Info: Back QL5032 - QuickPCI ESP 33 MHz/32-bit PCI Controller with Embedded Programmable Logic and Dual Port SRAM Advanced Data DEVICE HIGHLIGHTS Updated: 18-Dec-98 High Performance PCI Controller - 32-bit / 33 MHz Master/Target PCI Controller Zero-wait state PCI Master provides 132 MB/s transfer rates

T7035

Contextual Info: HIGH-SPEED 8 K x 18 DUAL-PORT STATIC RAM PRELIMINARY IDT7035S/L Features * * True Dual-Ported memory cells which allow simultaneous using the Master/Slave select when cascading more than reads of the same memory location one d e v ic e _ ♦ M/S = H for BUSY output flag on Master

Contextual Info: AN128 S OFTWARE SPI E XAMPLES FOR THE C8051F30 X F A M I L Y Introduction be skipped by the crossbar. Figure 1 shows the connections between the SPI master C8051F30x and This application note is a collection of routines that SPI slave devices. can be used to implement a master-mode SPI

7007S

Contextual Info: HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM IDT7007S/L Featu res * * * True Dual-Ported memory cells which allow simultaneous using the Master/Slave select when cascading more than reads of the same memory location one d e v ic e _ High-speed access M/S = H for BUSY output flag on Master,

16kx8 static ram ttl

Abstract: 2640I 08ND
Contextual Info: jg r -f HIGH-SPEED 32Kx 8 DUAL-PORT STATIC RAM PRELIMINARY IDT7007S/L In te g ra te d D evice T echnology, Inc. FEATURES: • IDT7007 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device • M/S= H for BUSY output flag on Master

9020

Abstract: intel 82596
Contextual Info: P L X TECHNOLOGY CORP 32E D • böSSm^ Q DD Q1 37 T *P L X T -5 2 -3 3 -5 5 EISA 9020 T ■ C H N O L O O V S' EISA Bus Master interface Chip for Intel 82596 LAN Controller Preliminary DECEMBER 1990 Features General Description EISA Bus Master Interface for

9020

Abstract: intel 82596 EISA 82596SX intel EISA Ethernet 82596
Contextual Info: P L X TECHNOLOGY CORP 32E D • böSSm^ Q DD Q1 37 T *P L X T -5 2 -3 3 -5 5 EISA 9020 T ■ C H N O L O O V S' EISA Bus Master interface Chip for Intel 82596 LAN Controller Preliminary DECEMBER 1990 Features General Description EISA Bus Master Interface for

83932

Abstract: 9010 plx LA 55-P DP83932 DP83934 EISA Bus Sonic DP83932 04/compaq eisa
Contextual Info: y P L X TECHNOLOGY CORP 52E » bflSSlM^ GGD0 3 4 4 b 45 IPLX E IS A 9 0 1 O B V EISA Bus Master Interface Chip for National SONIC-T DP83934 or SONIC DP83932 LAN Controller* September 1992 Patent Pending 'T " '5 2 . '3 3 - S 5 Features General Description * EISA Bus Master Interface for

ic isl 887

Abstract: T85 1e4 Switch TMS320C80 MP 1008 es MIP 289 C8050 AH-34 alu module for 32 bit processor GLC 555 texas instrument
Contextual Info: TMS320C80 DIGITAL SIGNAL PROCESSOR S P R S Q 2 3 A -JULY 1994 - R E VIS ED MARCH 1996 • Single-Chip Parallel Multiple Instruction/Multiple Data MIMD DSP • More Than Two Billion RISC-Equivalent Operations per Second • Master Processor (MP) - 32-Bit Reduced Instruction Set

vhdl code for usart

Abstract: atmel dac adc free vhdl code download for usart interrupt controller verilog code download spi bus arbiter ARM7TDMI communication peripherals ARM7TDMI interrupt controller vhdl code download advantages of microcontroller ARM microcontroller
Contextual Info: S YSTEM L EVEL I NTEGRATION ARM7TDMI MICROCONTROLLER CORE S YSTEM ARM7TDMI Test I/O Flash/ROM Program Embedded ICE ASB ARM Memory Controller ARM7TDMI Core ARM7TDMI Bus Interface External MCUs/DSPs EEPROM Data SRAM Workspace Bus Arbiter/ Master Signals Manager