RS FLIP FLOP Search Results

5 input nand gate

Abstract: 5 input nand gate dtl BL5D-7.9A DTL 950 DTL 9157 "NAND Gate"
Contextual Info: FAIRCHILD DIGITAL DTL DTL MICROLOGIC Item 1 Cont'd DEVICE NO. 948 Description RS Flip-Flop Logic/Connection Diagram Package(s) G18 3I,5F,6A,9A 2 949 Quad 2-Input NAND Gate G10 3I,5F,6A,9A 3 950 A-C Coupled RS Flip-Flop G19 3I,5F,6A,9A 4 951 M onostable M ultivibrator

DTL 9157

Abstract: DTL 950 5 input nand gate dtl DTL Fairchild 937 949 dtl 5 input nand gate DTL Fairchild DTL Fairchild 9109 936 dtl
Contextual Info: FAIRCHILD DIGITAL DTL DTL MICROLOGIC It m Cont’d DEVICE NO. Description Logic/Connection Diagram Packag (s) 1 948 RS Flip-Flop G18 3I,5F,6A,9A 2 949 Quad 2-Input NAND Gate G10 3I,5F,6A,9A 3 950 A-C Coupled RS Flip-Flop G19 3I,5F,6A,9A 4 951 Monostable Multivibrator

RS flip-flop

Abstract: 951 Monostable Multivibrator micrologic rs-flip-flop nand gate DTL Fairchild "power nand gate" 937 fairchild logic gate nand flip-flop 948
Contextual Info: FAIRCHILD DIGITAL - DTL DTL MICROLOGIC Item Cont’d Description DEVICE NO. Logic/Connection Diagram Package(s) 1 948 RS Flip-Flop G18

Contextual Info: 273 54F/74F273 Connection Diagrams Octal D Flip-Flop T— r ' - M R p ~ H rS rz a ht edge-triggered D-type flip-flops with individual D The common buffered Clock CP and Master Reset n ^ re s e i (clear) all flip-flops simultaneously. The register is full

Contextual Info: SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656C – FEBRUARY 2006 – REVISED APRIL 2007 FEATURES • • • • • • Choice of Three Phase Comparators – Exclusive OR – Edge-Triggered J-K Flip-Flop – Edge-Triggered RS Flip-Flop

74lv4046

Abstract: SN74LV4046AD LV4046A SN74LV4046A LV4046 SN74LV4046APWR
Contextual Info: SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656C – FEBRUARY 2006 – REVISED APRIL 2007 FEATURES • • • • • • Choice of Three Phase Comparators – Exclusive OR – Edge-Triggered J-K Flip-Flop – Edge-Triggered RS Flip-Flop

74lv4046

Contextual Info: SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656C – FEBRUARY 2006 – REVISED APRIL 2007 FEATURES • • • • • • Choice of Three Phase Comparators – Exclusive OR – Edge-Triggered J-K Flip-Flop – Edge-Triggered RS Flip-Flop

Contextual Info: SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656C – FEBRUARY 2006 – REVISED APRIL 2007 FEATURES • • • • • • Choice of Three Phase Comparators – Exclusive OR – Edge-Triggered J-K Flip-Flop – Edge-Triggered RS Flip-Flop

A115-A

Abstract: C101 CD4046B
Contextual Info: SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656C – FEBRUARY 2006 – REVISED APRIL 2007 FEATURES • • • • • • Choice of Three Phase Comparators – Exclusive OR – Edge-Triggered J-K Flip-Flop – Edge-Triggered RS Flip-Flop

LW046A

Abstract: A115-A C101 CD4046B
Contextual Info: SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656C – FEBRUARY 2006 – REVISED APRIL 2007 FEATURES • • • • • • Choice of Three Phase Comparators – Exclusive OR – Edge-Triggered J-K Flip-Flop – Edge-Triggered RS Flip-Flop

Contextual Info: SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656C – FEBRUARY 2006 – REVISED APRIL 2007 FEATURES • • • • • • Choice of Three Phase Comparators – Exclusive OR – Edge-Triggered J-K Flip-Flop – Edge-Triggered RS Flip-Flop

Contextual Info: SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656C – FEBRUARY 2006 – REVISED APRIL 2007 FEATURES • • • • • • Choice of Three Phase Comparators – Exclusive OR – Edge-Triggered J-K Flip-Flop – Edge-Triggered RS Flip-Flop

LW046A

Abstract: A115-A C101 CD4046B
Contextual Info: SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656C – FEBRUARY 2006 – REVISED APRIL 2007 FEATURES • • • • • • Choice of Three Phase Comparators – Exclusive OR – Edge-Triggered J-K Flip-Flop – Edge-Triggered RS Flip-Flop

LW046A

Contextual Info: SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656C – FEBRUARY 2006 – REVISED APRIL 2007 FEATURES • • • • • • Choice of Three Phase Comparators – Exclusive OR – Edge-Triggered J-K Flip-Flop – Edge-Triggered RS Flip-Flop

LW046A

Abstract: CD74HC4046
Contextual Info: SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656B – FEBRUARY 2006 – REVISED AUGUST 2006 FEATURES • • • • • • • Choice of Three Phase Comparators – Exclusive OR – Edge-Triggered J-K Flip-Flop – Edge-Triggered RS Flip-Flop

Contextual Info: SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656B – FEBRUARY 2006 – REVISED AUGUST 2006 FEATURES • • • • • • • Choice of Three Phase Comparators – Exclusive OR – Edge-Triggered J-K Flip-Flop – Edge-Triggered RS Flip-Flop

LW046A

Abstract: CD74HC4046 CD4046b A115-A C101 74lv4046 cd4046b application
Contextual Info: SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656A – FEBRUARY 2006 – REVISED FEBRUARY 2006 FEATURES • • • • • • • Choice of Three Phase Comparators – Exclusive OR – Edge-Triggered J-K Flip-Flop – Edge-Triggered RS Flip-Flop

cd74hc4046

Contextual Info: SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656A – FEBRUARY 2006 – REVISED FEBRUARY 2006 FEATURES • • • • • • • Choice of Three Phase Comparators – Exclusive OR – Edge-Triggered J-K Flip-Flop – Edge-Triggered RS Flip-Flop

LW046A

Contextual Info: SN74LV4046A HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO www.ti.com SCES656B – FEBRUARY 2006 – REVISED AUGUST 2006 FEATURES • • • • • • • Choice of Three Phase Comparators – Exclusive OR – Edge-Triggered J-K Flip-Flop – Edge-Triggered RS Flip-Flop

MAX202

Abstract: RS232 MAX202 MAX213 AN441 APP4417 MAX200 MAX211 4-417
Contextual Info: Maxim > App Notes > Power-Supply Circuits Keywords: RS-232 transceiver, bipolar supply rails, charge pumps, flip-flops Aug 06, 2009 APPLICATION NOTE 4417 Transceiver IC Generates ±30V By: Nick Allen-Rowlandson Zeeshawn Shameem Abstract: This application note explains how an RS-232 transceiver and a few external components can be

IC 74175

Abstract: H1322 sylvania logic
Contextual Info: Sylvania ECG Sem ico nd ucto rs ECG74174, LS174, S174, 74175, LS175, S175 Hex/Quad D Flip-Flops with Clear These positive-edge-triggered flip-flop s u tilize T T L c irc u itry to im plem ent D t y p e flip -flo p logic. A ll have a d ire ct clear in p u t, and the quad 1 7 5 versions feature

74F109

Abstract: 74LS245N I74F109D I74F109N N74F109D N74F109N
Contextual Info: Product specification Philips S em ico n d u cto rs-S ig n e tics FAST Products Positive J -K positive edge-triggered flip-flops FEATURE TYPE • Industrial temperature range available -40°C to +85°C 74F109 DESCRIPTION The 74F109 is a dual positive edgetriggered JK-type flip-flop featuring in­

54F109

Abstract: GDFP2-F16 GDIP1-T16 S54C
Contextual Info: P ro d u ct sp ecifica tio n P h ilip s S e m ic o n d u c to rs M ilitary F A S T P ro d u cts Flip-flop 54F109 Th e J K design allow s operation a s a D flip-flop by tying the J and K inputs together. DESCRIPTION Th e 54 F109 is a dual positive edge-triggered JK-type flip-flop

7496 truth table

Abstract: 7496 7496 5-bit shift right shift register 9396 9396 7496 ScansUX991
Contextual Info: TTL/MSI 9396/5496, 7496 5—BIT SHIFT REGISTER DESCRIPTION - The TTL/MSI 9396/5496, 7496 5-Bit Shift Register consists of five RS master/ slave flip-flops connected to perform parallel-to-serial or serial-to-parallel conversion of binary data. Since both inputs and outputs to all flip-flops are accessible, parallel-in/parallel-out or