RES ARRAY 4 Search Results

Contextual Info: 28LV011 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 28LV011 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch

Contextual Info: HEWLETT PA CK A RD m 10-Element Bar Graph Array Technical Data HLCP-J100 H DSP-4820 H DSP-4830 HDSP-4832 F eatu res D escription • Custom M ulticolor Array Capability • M atched LEDs for Uniform Appearance • End Stackable • Package Interlock E nsures

PLANAR

Abstract: 16X16
Contextual Info: Cableless TV Patch Planar Arrays 16 x 16 Element Planar Patch Array F eatu res > Small Size I C om pact I Low-Profile I Rugged S p ecificatio n s Frequency Range 27.5 - 28.5 GHz Size 4.5 x 4.5 Inches Beamwidth -3 dB Nominal 5° Type 16x16 Element Planar Array

28C010T

Contextual Info: 28C011T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 28C011T Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch Memory

28LV010

Contextual Info: 28LV010 3.3V 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE WE Control Logic Timing RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch FEATURES:

32-PIN RAD-PAK FLAT PACKAGE

Abstract: 28C010T 28C011T 32-PIN
Contextual Info: 28C011T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 28C011T Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch Memory

128k x 8 eeprom

Contextual Info: 28LV010 3.3V 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE WE Control Logic Timing RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch FEATURES:

F3205

Abstract: 32-PIN RAD-PAK FLAT PACKAGE tdb 0117
Contextual Info: 28C011T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch FEATURES:

28 pin 128k eeprom

Contextual Info: 28LV010 3.3V 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE WE Control Logic Timing RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch FEATURES:

Contextual Info: 28LV010 3.3V 1 Megabit 128K x 8-Bit EEPROM VCC VSS High Voltage Generator I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE WE Control Logic Timing RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch FEATURES:

28C011T

Abstract: 32-PIN tdb 0117
Contextual Info: 28C011T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch FEATURES:

d32-02

Abstract: 28C010T 32-PIN
Contextual Info: 28C010T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 Memory A16 Data Latch FEATURES:

28C011T

Abstract: 32-PIN 28C011
Contextual Info: 28C011T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch FEATURES:

28C010T - 12

Abstract: 28c010T
Contextual Info: 28C010T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch Memory Logic Diagram

F3208

Contextual Info: 28C010T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE WE Control Logic Timing RES A0 Y Decoder Y Gating X Decoder Memory Array A6 A7 Address Buffer and Latch A16 Memory Data Latch FEATURES:

Contextual Info: 28LV010 3.3V 1 Megabit 128K x 8-Bit EEPROM VCC VSS High Voltage Generator I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE WE Control Logic Timing RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch FEATURES:

Maxwell

Abstract: 28C010T 32-PIN 28C010
Contextual Info: 28C010T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch Memory Logic Diagram

Contextual Info: 28C010T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch Memory Logic Diagram

28C010T

Abstract: 32-PIN D32-02
Contextual Info: 28C010T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch Memory Logic Diagram

Contextual Info: 28C010T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch Memory Logic Diagram

Contextual Info: 28C010T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch Memory Logic Diagram

Contextual Info: CRA06P Vishay Dale Thick Film Resistor Array FEA TU RES • 8 terminal package with 4 isolated resistors. • Automatic placem ent capability. • Flow solderable. • Inner electrode protection. • Thick film resistance element. • W rap around termination.

pin configuration of 7486 IC

Abstract: pin DIAGRAM OF IC 7486 pin configuration OF IC 7486 IC 7486 MC6809 package 7486 ic truth table connection diagram IC 7486 DIAGRAM OF IC 7486 ic 7409 TTL 7486
Contextual Info: MT88V32 8 x 4 High Performance Video Switch Array M ITEL Prelim inary Inform ation F e atu res ISSUE 1 August 1993 O rdering Inform ation 32 bidirectional CM OS "T" sw itches in an 8 x 4 non-blocking array M T88V32AP 44 Pin PLCC -40° to 85°C B reak-before-m ake sw itching configuration

Contextual Info: Preliminary Data INTERNATIONAL CMOS TECHNOLOGY, INC. INTERNATIONAL C M O S 37E D H March 1991 4640707 0D0043T 1 IS ICT PEEL 22CV10A CMOS Programmable Electrically Erasable Logic Device Featu res ^ ^ ^ ~<^~7 Architectural Flexibility — 132 product term x 44 input AND array