RES ARRAY 4 Search Results

Contextual Info: 28LV011 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 28LV011 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch

Contextual Info: HEWLETT PA CK A RD m 10-Element Bar Graph Array Technical Data HLCP-J100 H DSP-4820 H DSP-4830 HDSP-4832 F eatu res D escription • Custom M ulticolor Array Capability • M atched LEDs for Uniform Appearance • End Stackable • Package Interlock E nsures

PLANAR

Abstract: 16X16
Contextual Info: Cableless TV Patch Planar Arrays 16 x 16 Element Planar Patch Array F eatu res > Small Size I C om pact I Low-Profile I Rugged S p ecificatio n s Frequency Range 27.5 - 28.5 GHz Size 4.5 x 4.5 Inches Beamwidth -3 dB Nominal 5° Type 16x16 Element Planar Array

28C010T

Contextual Info: 28C011T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 28C011T Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch Memory

32-PIN RAD-PAK FLAT PACKAGE

Abstract: 28C010T 28C011T 32-PIN
Contextual Info: 28C011T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 28C011T Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch Memory

F3205

Abstract: 32-PIN RAD-PAK FLAT PACKAGE tdb 0117
Contextual Info: 28C011T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch FEATURES:

28 pin 128k eeprom

Contextual Info: 28LV010 3.3V 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE WE Control Logic Timing RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch FEATURES:

28C010T - 12

Abstract: 28c010T
Contextual Info: 28C010T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch Memory Logic Diagram

28LV010

Abstract: tdb 0117
Contextual Info: 28LV011 3.3V 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE WE Control Logic Timing RES 28LV011 A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch

F3208

Contextual Info: 28C010T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE WE Control Logic Timing RES A0 Y Decoder Y Gating X Decoder Memory Array A6 A7 Address Buffer and Latch A16 Memory Data Latch FEATURES:

Contextual Info: 28LV010 3.3V 1 Megabit 128K x 8-Bit EEPROM VCC VSS High Voltage Generator I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE WE Control Logic Timing RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch FEATURES:

Maxwell

Abstract: 28C010T 32-PIN 28C010
Contextual Info: 28C010T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch Memory Logic Diagram

Contextual Info: 28C010T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch Memory Logic Diagram

Contextual Info: 28C010T 1 Megabit 128K x 8-Bit EEPROM VCC High Voltage Generator VSS I/O0 I/O7 RDY/Busy RES I/O Buffer and Input Latch OE CE Control Logic Timing WE RES A0 Y Decoder Y Gating X Decoder Memory Array A6 Address Buffer and Latch A7 A16 Data Latch Memory Logic Diagram

Contextual Info: CRA06P Vishay Dale Thick Film Resistor Array FEA TU RES • 8 terminal package with 4 isolated resistors. • Automatic placem ent capability. • Flow solderable. • Inner electrode protection. • Thick film resistance element. • W rap around termination.

Contextual Info: Preliminary Data INTERNATIONAL CMOS TECHNOLOGY, INC. INTERNATIONAL C M O S 37E D H March 1991 4640707 0D0043T 1 IS ICT PEEL 22CV10A CMOS Programmable Electrically Erasable Logic Device Featu res ^ ^ ^ ~<^~7 Architectural Flexibility — 132 product term x 44 input AND array

Contextual Info: CML Semiconductor Products csjnyn PRODUCT INFORMATION ry o ^ c • A O ^ IO G AMPS, TACS, NMT Audio Processing Array Publication D/346/4 December 1991 Provisional Issue Featu res/Appi ¡cations • AMPS, TACS, NMT Audio + Data Processing • Speech, SAT and Data - Full

Contextual Info: SIEMENS KOM 2085 4-CHIP SILICON PIN PHOTODIODE ARRAY Package Dimensions in mm Transparent Schematic K A2o-t¡l-to-oA1 A3o-C+- -KJ-o A4 FEA TU RES Characteristics, Single Segment TA=25°C, std. light A, T=2856 K * Silicon Photodiode in Planar Technology

3300W

Contextual Info: Semicustom Products UTB Series Gate Array Family Preliminary Data Sheet UNITED TECHNOLOGIES MICROELECTRONICS CENTER FEA TU RES □ Designed for military/aerospace applications - Operating range: —55 °C to 125° C - Supply voltage: 5V ± 10% - ESD protection: 2001 V minimum

Contextual Info: fax id: 6102 CY7C343 CY7C343B 64-Macrocell MAX EPLD Functional Description Featu res • 64 MAX macrocells in 4 LABs • 8 dedicated inputs, 24 bidirectional I/O pins • Programmable interconnect array The CY7C343/CY7C343B is a high-performance, high-density erasable programmable logic device, available in 44-pin

array resistor

Abstract: CAY10
Contextual Info: December, 2005 Reliable Electronic Solutions Manufacturers Representatives Corporate Distributor Product Managers Americas Sales Team Asia Sales Team Europe Sales Team S RAY R P I A CH TOR IS RES Bourns Networks Product Line Announces Revision to Marking of Model CAY10 Chip Resistor Array

Contextual Info: fax id: 6006 This is an abbreviated datasheet. Contact a Cypress repre­ sentative for complete specifications. For new designs, please refer to the PALCE22V10 PALC22V10B Reprogrammable CMOS PAL Device — Phantom array Featu res — Top test • Advanced second generation PAL architecture

Contextual Info: ^EDI EDI784MSV-RP ELECTRONIC DESIGNS. INC 4Megx8 Ruggedized Plastic NAND Flash 4Mx8 Bit NAND Flash CMOS, Monolithic F eatu res The EDI784MSV is a 4M 4,194,304 x8 bit Ruggedized Plastic NAND Flash memory with a spare array of 128K(131,072)x8 bit. Its NAND cell provides the most cost-effective solution for high

Contextual Info: EEPROM AS8ER128K32 Austin Semiconductor, Inc. 128K x 32 EEPROM PIN ASSIGNMENT Radiation Tolerant EEPROM Memory Array Top View 68 Lead CQFP • RES\ A0 A1 A2 A3 A4 A5 CS3\ GND CS4\ WE1\ A6 A7 A8 A9 A10 Vcc AVAILABLE AS MILITARY SPECIFICATIONS MIL-STD-883