REGISTERED BUFFER PARITY Search Results
REGISTERED BUFFER PARITY Equivalents
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REGISTERED BUFFER PARITY Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
|---|---|---|---|---|---|
| SF-10GSFPPLCL-000 |
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Amphenol SF-10GSFPPLCL-000 SFP+ Optical Module - 10GBASE-SR (up to 300m/984') SFP+ Multimode Optical Transceiver Module (Duplex LC Connectors) - Cisco & HP Compatible | |||
| SF-QXP85B402D-000 |
|
Amphenol SF-QXP85B402D-000 QSFP28 100GBASE-SR Short-Range 850nm Multi-Mode Optical Transceiver Module (MTP/MPO Connector) by Amphenol XGIGA [QXP85B402D] | |||
| SF-XP85B102DX-000 |
|
Amphenol SF-XP85B102DX-000 SFP28 25GBASE-SR Short-Range 850nm Multi-Mode Optical Transceiver Module (Duplex LC Connector) by Amphenol XGIGA [XP85B102DX] | |||
| 74HC595D |
|
CMOS Logic IC, 8-bit Shift Register, SOIC16, -40 to 125 degC | Datasheet | ||
| 74VHC541FT |
|
CMOS Logic IC, Octal Buffer, TSSOP20B | Datasheet |
REGISTERED BUFFER PARITY Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
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Contextual Info: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTU32865 FEATURES: DESCRIPTION: • • • • • • • The SSTU32865 is a 28-bit 1:2 configurable registered buffer designed |
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IDT74SSTU32865 28-BIT IDT74SSTU32865 100mA MIL-STD-883, 200pF, 160-pin SSTU32865 | |
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Contextual Info: IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST 1.8V CONFIGURABLE BUFFER WITH ADDRESSPARITY TEST 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input Configurable as 25-bit 1:1 or 14-bit 1:2 registered buffer |
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IDT74SSTUA32866 25-bit 14-bit 100mA MIL-STD-883, 200pF, 410MHz 96-pin 10MHz, | |
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Contextual Info: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FEATURES: IDT74SSTU32865 DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input |
Original |
IDT74SSTU32865 28-BIT IDT74SSTU32865 100mA MIL-STD-883, 200pF, 160-pin CSPU877/A/D DDR2-400/533 | |
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Contextual Info: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FEATURES: IDT74SSTU32865 DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input |
Original |
IDT74SSTU32865 28-BIT 100mA MIL-STD-883, 200pF, 160-pin SSTU32865 | |
silego
Abstract: Silego Technology DDR2-800 buffer marking code D22 q28b SILEGO q27b Q24A Q17B
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SLGSSTUB32868 DDR2-800 28-bit, 420MHz 176-BGA SLGSSTUB32868 silego Silego Technology buffer marking code D22 q28b SILEGO q27b Q24A Q17B | |
IDT74SSTU32865
Abstract: SSTU32865
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IDT74SSTU32865 28-BIT 100mA MIL-STD-883, 200pF, 160-pin SSTU32865 IDT74SSTU32865 | |
silego
Abstract: Silego Technology D8-D13 D8-D25 Q11A SSTUB32866 lfbga-96ball SLGSSTUB32866B
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SLGSSTUB32866 DDR2-400/533/667/800 25-bit 14-bit SSTUB32866 410MHz 96-LFBGA SLGSSTUB32866 silego Silego Technology D8-D13 D8-D25 Q11A SSTUB32866 lfbga-96ball SLGSSTUB32866B | |
D869Contextual Info: IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 14-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTU32D869 FEATURES: • • • • • • • • 1.8V Operation Designed to drive low impedance nets SSTL_18 style clock and data inputs |
Original |
IDT74SSTU32D869 14-BIT IDT74SSTU32D869 100mA MIL-STD-883, 200pF, 150-pin CSPU877/A/D DDR2-400/533 D869 | |
D869
Abstract: marking nb IDT74SSTU32D869
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IDT74SSTU32D869 14-BIT 100mA MIL-STD-883, 200pF, 150-pin 10MHz, D869 marking nb IDT74SSTU32D869 | |
d869
Abstract: ef2 marking
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IDT74SSTU32D869 14-BIT IDT74SSTU32D869 100mA MIL-STD-883, 200pF, 150-pin 10MHz, d869 ef2 marking | |
ICS98ULPA877A
Abstract: ICSSSTUAF32866C IDTCSPUA877A
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ICSSSTUAF32866C 25-BIT ICSSSTUAF32866C 14-bit 199707558G ICS98ULPA877A IDTCSPUA877A | |
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Contextual Info: DATASHEET IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the IDT74SSTUBF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is |
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IDT74SSTUBF32866B 25-BIT IDT74SSTUBF32866B 14-bit 199707558G | |
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Contextual Info: DATASHEET IDT74SSTUAE32866A 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.425V to 1.575V VDD operation. |
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IDT74SSTUAE32866A 25-BIT 14-bit sam284 199707558G | |
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Contextual Info: DATASHEET ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the ICSSSTUAF32866C must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is |
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ICSSSTUAF32866C 25-BIT ICSSSTUAF32866C 14-bit 199707558G | |
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ICS98ULPA877A
Abstract: ICSSSTUAF32866B IDTCSPUA877A
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ICSSSTUAF32866B 25-BIT ICSSSTUAF32866B 14-bit 199707558G ICS98ULPA877A IDTCSPUA877A | |
ICS98ULPA877A
Abstract: ICSSSTUAF32866C IDTCSPUA877A
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ICSSSTUAF32866C 25-BIT ICSSSTUAF32866C 14-bit 199707558G ICS98ULPA877A IDTCSPUA877A | |
7120
Abstract: ICS98UAE877A IDT74SSTUAE32866A Q11A
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IDT74SSTUAE32866A 25-BIT 14-bit sam284 199707558G 7120 ICS98UAE877A IDT74SSTUAE32866A Q11A | |
ICS98ULPA877A
Abstract: ICSSSTUAF32866B IDTCSPUA877A
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ICSSSTUAF32866B 25-BIT ICSSSTUAF32866B 14-bit 199707558G ICS98ULPA877A IDTCSPUA877A | |
ICS98ULPA877A
Abstract: IDT74SSTUBF32866B IDTCSPUA877A Q11A
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IDT74SSTUBF32866B 25-BIT IDT74SSTUBF32866B 14-bit 199707558G ICS98ULPA877A IDTCSPUA877A Q11A | |
ICS98ULPA877A
Abstract: ICSSSTUAF32866C IDTCSPUA877A
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Original |
ICSSSTUAF32866C 25-BIT ICSSSTUAF32866C 14-bit 199707558G ICS98ULPA877A IDTCSPUA877A | |
ICS98ULPA877A
Abstract: IDT74SSTUBF32866B IDTCSPUA877A Q11A
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IDT74SSTUBF32866B 25-BIT IDT74SSTUBF32866B 14-bit 199707558G ICS98ULPA877A IDTCSPUA877A Q11A | |
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Contextual Info: DATASHEET IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the IDT74SSTUBF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is |
Original |
IDT74SSTUBF32866B 25-BIT IDT74SSTUBF32866B 14-bit 199707558G | |
EA32882B
Abstract: SSTE32882
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Original |
SN74SSQEA32882 SCAS879 28-BIT 56-BIT SSTE32882 EA32882B | |
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Contextual Info: SN74SSTEB32866 www.ti.com. SCAS851 – APRIL 2009 1.5V/1.8V 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST |
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SN74SSTEB32866 SCAS851 25-BIT 14-Bit | |