RANT Search Results

STW6NA90

Abstract: sd 50 diode
Contextual Info: STW6NA90 N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR PRELIMINARY DATA TYPE STW6NA90 • ■ ■ ■ ■ ■ ■ V DSS R DS on ID 900 V < 1.9 Ω 6A TYPICAL RDS(on) = 1.45 Ω ± 30V GATE TO SOURCE VOLTAGE RANTING 100% AVALANCHE TESTED REPETITIVE AVALANCHE DATA AT 100oC

STU6NA100

Contextual Info: STU6NA100 N - CHANNEL 1000V - 1.45Ω - 6A - Max220 FAST POWER MOS TRANSISTOR PRELIMINARY DATA TYPE STU6NA100 • ■ ■ ■ ■ ■ ■ V DSS R DS on ID 1000 V < 1.7 Ω 6A TYPICAL RDS(on) = 1.45 Ω ± 30V GATE TO SOURCE VOLTAGE RANTING 100% AVALANCHE TESTED

STU7NA90

Abstract: sd 50 diode
Contextual Info: STU7NA90 N - CHANNEL 900V - 1.05 Ω - 7A - Max220 FAST POWER MOS TRANSISTOR PRELIMINARY DATA TYPE V DSS R DS on ID STU7NA90 900 V < 1.3 Ω 7A • ■ ■ ■ ■ ■ ■ TYPICAL RDS(on) = 1.05 Ω ± 30V GATE TO SOURCE VOLTAGE RANTING 100% AVALANCHE TESTED

LT6350

Abstract: LTC2391-16 LTC2392-16 LTC2393 LTC2393-16
Contextual Info: LTC2393-16 16-Bit 1Msps SAR ADC 125°C + o t C – 40° ranteed Gua 4.096V 5V IN+ OVDD = 1.8V to 5V LTC2393-16 IN– SPI or Parallel Internal Reference 4.096V Wide Fully Differential Input Range Achieves 94.2dB SNR High SNR is achieved with a ±4.096V maximum signal swing that helps overcome background noise levels in demanding

Contextual Info: In fo rm atio n furnished by R C A is believed to be accurate and reliable. How ever, no responsibility is assum ed by R C A fo r its use; n o r for a n y infringem ents of paten ts or o th er rights o f th ird parties w hich m ay result from its use. N o license is g ranted by im plication

U6NA100

Abstract: STU6NA100
Contextual Info: STU6NA100  N - CHANNEL 1000V - 1.45Ω - 6A - Max220 FAST POWER MOS TRANSISTOR PRELIMINARY DATA TYPE ST U6NA100 • ■ ■ ■ ■ ■ ■ V DSS R DS on ID 1000 V < 1.7 Ω 6A TYPICAL RDS(on) = 1.45 Ω ± 30V GATE TO SOURCE VOLTAGE RANTING 100% AVALANCHE TESTED

program delphi

Abstract: software delphi DLL4882 ni application note ni488 NI-488
Contextual Info: Application Note 085 Using NI-488.2M Software with 32-Bit Delphi Applications L. Rantanen Introduction Borland Delphi version 2.0 , one of the latest visual programming languages, uses Rapid Application Development (RAD) tools. With RAD tools, one can quickly and easily create Windows applications. Delphi is based on Object

20V8

Abstract: GAL20LV8 GAL20LV8D-3LJ GAL20LV8D-5LJ GAL20LV8D-7LJ simple diagram for electronic clock
Contextual Info: Ne Tolew 5V Inp rant u 20L ts on V8D GAL20LV8 Functional Block Diagram Features • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 2.5 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology

Contextual Info: HçyUiniûtîtfc’ 1 A L O U T P U T PEN TO D E P E N T H O D E D E S O R T IE P E N T H O D E -E N D R O E H R E H e a rin g : Chauffage : H eizung : In d ir e c t ; A .C .; parallel supply In d ire c t ; cou rant a lte rn a tif ; alim entation en parallèle

Contextual Info: Zjï SGS-THOMSON ¡ILIOTI^OKinei STW6NA90 N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR PRELIMINARY DATA TYPE V dss STW 6NA90 900 V R d S oii Id a 6 A < 1 .9 . TYPICAL RDs(on) = 1.45 £2 . ± 30V GATE TO SOURCE VOLTAGE RANTING . 100% AVALANCHE TESTED

Contextual Info: STU7NA90 N - CHANNEL 900V - 1.05 £2 - 7A - Max220 FAST POWER MOS TRANSISTOR PRELIMINARY DATA TYPE V dss R d S oii STU 7N A 90 900 V < 1.3 a Id 7 A TYPICAL R D S (on) = 1.05 . ± 30V GATE TO SOURCE VOLTAGE RANTING . 100% AVALANCHE TESTED . REPETITIVE AVALANCHE DATA AT 100°C

D1985

Contextual Info: y k iy jx iw i Quad SPST CMOS Analog Sw itches _ . The MAX332 and DG202/DG212 are sim ilar to the DG201 and DG211 except fo r inverted co n tro l inputs. A ll devices have g u a ranteed b re a k-b e fo re -m a ke sw itching as well as essentially constant on resistance

X318

Abstract: X319 X31C MAX319MJA X317 MAX319ESA T AX318 AX319 MAX318CPA
Contextual Info: 1 9-0185; R e v 0; 9 /9 3 Precision, CMOS Analog S w itches T he M A X 3 1 7 /M A X 3 1 8 /M A X 3 1 9 a re fa b ric a te d w ith M axim 's new im p ro ve d silico n -g a te p rocess. Design im p ro ve m en ts g u a rantee extrem ely low ch a rg e in je c­

HK6201

Contextual Info: Am «p no o oondMon fc a f V • not to b t 4M m m I. nproduowl o r UMd. tn ■ M i o r In port, fo r manufooM « o r o h by anyono oMm t than Amphonoi C enm H an wWiout h pdor eaneart, f t th a t no ngM b ranted to oM m * o r to uoo any tirform cwon to Hit» rio om rant._

20V8

Abstract: GAL20LV8 GAL20LV8D-3LJ GAL20LV8D-5LJ GAL20LV8D-7LJ
Contextual Info: GAL20LV8 Ne Tolew 5V Inp rant u 20L ts on V8D Low Voltage E2CMOS PLD Generic Array Logic Functional Block Diagram Features • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 2.5 ns Maximum from Clock Input to Data Output

2T3604

Abstract: L73L 2T3605 2T3606 2t3607 H21E rouge 2T3604 2T3605 2T3606 2T3607 ScansUX7 h21E1
Contextual Info: VRAnilfTORf TYPE n-p-n A ll SILICIUM P L A N A R S -E P IT A X IA U X DE COMMUTATION RAPIDE /E D S 11508-73/ 1. Corps on matière plastique TO-92 2. Valeurs g.i ranties sous Tam ^ ^ /2 5 i 2/°C Espèce U n ité P a ra m è tre de Régim e de v a le u r mesure

state variable filter

Abstract: AN797 BI-QUAD RC Active Bandpass Filter AN-797
Contextual Info: AN-797 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781/329-4700 • Fax: 781/461-3113 • www.analog.com Quad Precision Op Amp Evaluation Board by Giampaolo Marino and Steve Ranta INTRODUCTION The EVAL-PRAOPAMP- 4R/4RU is an evaluation board

GAL programmer schematic

Abstract: GAL22LV10D-4LJ GAL22LV10D-5LJ GAL22LV10 GAL22LV10C GAL22LV10C-10LJ GAL22LV10C-15LJ GAL22LV10C-7LJ
Contextual Info: Ne Tolew 5V Inp rant 22Luts on V10 D Features GAL22LV10 Low Voltage E2CMOS PLD Generic Array Logic Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 4 ns Maximum Propagation Delay — Fmax = 250 MHz — 3 ns Maximum from Clock Input to Data Output

HP5082-2811

Abstract: HP5082 hp50822811 hp5082 diode 1AAA AD7533UD/883B AD7533TD/883B AD7533 AD7533JN AD7533KN
Contextual Info: ANALOG DEVICES □ CM0S Low Cost 10-B'it Multiplying DAC P R E L IM IN A R Y TE C H N IC A L DATA FEATURES Lowest Cost 10 Bit D A C Direct A D 7 5 2 0 Equivalent L ire a rity 1 or 2LSB Low Power Dissipation Full F o u r-Qu ad rant M u ltip ly in g D<\C C M O S /T T L Direct Interface

GAL22LV10C-10LJ

Abstract: GAL22LV10C-15LJ GAL22LV10D-4LJ GAL22LV10D-5LJ GAL22LV10 GAL22LV10C
Contextual Info: Ne Tolew 5V Inp rant 22Luts on V10 D GAL22LV10 Low Voltage E2CMOS PLD Generic Array Logic Functional Block Diagram Features • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 4 ns Maximum Propagation Delay — Fmax = 250 MHz — 3 ns Maximum from Clock Input to Data Output

TIC 136 Transistor

Contextual Info: STU6NA100 N - CHANNEL 1000V - 1 .45ß - 6A - Max220 FAST POWER MOS TRANSISTOR PRELIMINARY DATA TYPE V dss S T U 6N A 100 1000 V R dS oii Id a 6 A < 1 .7 . TYPICAL RDs(on) = 1.45 £2 . ± 30V GATE TO SOURCE VOLTAGE RANTING . 100% AVALANCHE TESTED . REPETITIVE AVALANCHE DATA AT 100°C

Contextual Info: Zjï SGS-THOMSON ¡ILIOTI^OKinei S T W 16N A 60 N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR PRELIMINARY DATA TYPE STW 16N A 60 V dss R d S oii Id 600 V < 0.4 a 16 A • TYPICAL RDS(on) = 0.33 . ± 30V GATE TO SOURCE VOLTAGE RANTING . 100% AVALANCHE TESTED

pin details of ic 2561

Abstract: ttl XOR gate circuit IC of XOR GATE 20V8 GAL20LV8 GAL20LV8D-3LJ GAL20LV8D-5LJ GAL20LV8D-7LJ G20V8A
Contextual Info: Ne Tolew 5V Inp rant u 20L ts on V8D GAL20LV8 Low Voltage E2CMOS PLD Generic Array Logic Functional Block Diagram Features • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 2.5 ns Maximum from Clock Input to Data Output

STW16NA60

Contextual Info: STW16NA60 N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR PRELIMINARY DATA TYPE STW16NA60 • ■ ■ ■ ■ ■ ■ V DSS R DS on ID 600 V < 0.4 Ω 16 A TYPICAL RDS(on) = 0.33 Ω ± 30V GATE TO SOURCE VOLTAGE RANTING 100% AVALANCHE TESTED REPETITIVE AVALANCHE DATA AT 100oC