RAD DATA COMMUNICATIONS Search Results

Contextual Info: RAD Line IO BD RAD Line IO – Bidirectional wireless transmission system Data sheet 2858_en_C 1 PHOENIX CONTACT 2012-11-06 Description The RAD-ISM-900-SET…BUS… bidirectional wireless systems are pre-programmed sets of transceivers capable of transmitting and receiving wireless signals and ready for

HMX9225

Abstract: rad analog to digital converter 14 bit
Contextual Info: HMXADC9225 Radiation Hardened 12-Bit, 20 MSPS Monolithic A/D Converter Features Monolithic 12-Bit, 20 MSPS A/D Converter n Rad Hard: >500k Rad Si Total Dose n Single +5 V Analog Supply n Complete On-Chip S/H Amplifier n Straight Binary Output Data n 5V or 3.3V Digital and I/O Supply

2E12

Abstract: FSS13A0D FSS13A0D1 FSS13A0D3 FSS13A0R FSS13A0R1 FSS13A0R3 Rad hard for Harris
Contextual Info: FSS13A0D, FSS13A0R Data Sheet 2A, 100V, 0.170 Ohm, Rad Hard, SEGR Resistant, N-Channel Power MOSFETs The Discrete Products Operation of Harris Semiconductor has developed a series of Radiation Hardened MOSFETs specifically designed for commercial and military space

Contextual Info: M672061F 16 K  9 CMOS With Programmable Half Full Flag Parallel FIFO Rad Tolerant Description The M672061F implements a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow.

M672061E

Abstract: M672061F
Contextual Info: M672061F 16 K  9 CMOS With Programmable Half Full Flag Parallel FIFO Rad Tolerant Description The M672061F implements a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow.

Andrew RADIAx

Abstract: andrew gsm FOAM FEP TETRA Andrew RADIAX RXL-4
Contextual Info: RAD IAX Cable Underground Systems RADIAX cable was developed with tunnels in mind. Long, narrow corridors require the continous coverage RADIAX provides. This topology improves the efficiency of data transfer times as opposed to every user operating from the same

M672061E

Contextual Info: M672061E 16 K  9 CMOS With Programmable Half Full Flag Parallel FIFO Rad Tolerant Description The M672061E implements a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow.

Contextual Info: DATA SHEET VITESSE FX~MFam ily " " “ SEMICONDUCTOR CORPORATION H igh P erform ance G ate Arrays for M ilitary Applications Features • Superior Performance: High Speed and Low Power Dissipation • Mature, Rad iation Hard, GaAs Enhancement/ Depletion M ESFET Process

fifo buffer empty full flag error reset

Abstract: M67206 M672061E
Contextual Info: Tem ic M672061E Semiconductors 16 K x 9 CMOS With Programmable Half Full Flag Parallel FIFO Rad Tolerant Description The M672061E implements a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow.

M67204E

Abstract: fifo read write pointer depth expansion
Contextual Info: M67204E 4 K  9 CMOS Parallel FIFO Rad Tolerant Introduction The M67204E implement a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word

M67204E

Contextual Info: M67204E 4 K  9 CMOS Parallel FIFO Rad Tolerant Introduction The M67204E implement a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word

M67204E

Contextual Info: M67204E 4 K  9 CMOS Parallel FIFO Rad Tolerant Introduction The M67204E implement a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word

M67204F

Abstract: 67204F
Contextual Info: M67204F 4 K  9 High Speed CMOS Parallel FIFO Rad Tolerant Introduction The M67204F implements a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word

depth expansion fifo pointer read write

Abstract: M67204E
Contextual Info: Temic M67204E Semiconductors 4 K x 9 CMOS Parallel FIFO Rad Tolerant Introduction The M67204E implement a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word

Contextual Info: RAD-900-IFS 900 MHz wireless transceiver transmitter and receiver with RS-232 and RS-485 interface, can be extended with I/O extension modules Data sheet 3225_en_D 1 PHOENIX CONTACT 2014-01-21 Description Wireless communication is based on Trusted Wireless 2.0

M67206E

Abstract: M67206F
Contextual Info: M67206F 16 K  9 High Speed CMOS Parallel FIFO Rad Tolerant Introduction The M67206F implements a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word

M67206E

Contextual Info: M67206E 16 K  9 High Speed CMOS Parallel FIFO Rad Tolerant Introduction The M67206E implements a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word

67204F

Contextual Info: M67204F 4 K  9 High Speed CMOS Parallel FIFO Rad Tolerant Introduction The M67204F implements a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word

Contextual Info: SGS-THOMSON raD»HlLll Ê'inM l)i!lD(ei S T95022 2K SERIAL SPI EEPROM with HIGH SPEED CLOCK • HIGH SPEED CLOCK RATE: - 2.1 MHz Max ■ 1,000,000 ERASE/WRITE CYCLES > 40 YEARS DATA RETENTION > SINGLE 4.5V to 5.5V SUPPLY VOLTAGE > SPI BUS COMPATIBLE SERIAL INTERFACE

Contextual Info: DATA SHEET VITESSE FX-M Family High Performance Gate Arrays for Military Applications SEMICONDUCTOR CORPORATION Features • Superior Perform ance: High Speed and Low Pow er Dissipation 5 Arrays from 20K to 35 0 K Gates • Mature, Rad iation Hard, G aA s E nhancem ent/

CLC402A

Abstract: CLC400 CLC402 CLC402AJFQML CLC402AJ-QML MNCLC402A-X-RH
Contextual Info: MICROCIRCUIT DATA SHEET Original Creation Date: 05/16/00 Last Update Date: 05/31/00 Last Major Revision Date: MNCLC402A-X-RH REV 0A0 LOW-GAIN OP AMP WITH FAST 14-BIT SETTLING: ALSO AVAILABLE GUARANTEED TO 300K RAD Si TESTED TO MIL-STD-883, METHOD 1019.5 General Description

Contextual Info: ‘ lira % i 1992 DATA SHEET VITESSE SEMICONDUCTOR CORPORATION FX-M Family High Performance Gate Arrays for M ilitary Applications Features • Superior Perform ance: High Speed and Low Power Dissipation • Mature, Rad iation Hard, G aA s Enhancem ent/ Depletion M E S F E T Process

fifo buffer empty full flag error reset

Abstract: M672061 M67206E 7206I
Contextual Info: Temic M67206E S e m i c o n d u c t o r s 16 K x 9 High Speed CMOS Parallel FIFO Rad Tolerant Introduction The M67206E implements a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow.

Contextual Info: RHFLVDS228A Rad-hard, dual 4x4 crosspoint switch LVDS Datasheet - production data • Large input common mode: -4 V to +5 V • Guaranteed up to 300 krad TID • SEL immune up to 135 MeV.cm²/mg • SET/SEU immune up to 22 MeV.cm²/mg Description The RHFLVDS228A is an 8-channel, 4x4