RABU Search Results

Am79C83

Contextual Info: Am79C83 Fiber Optic Ring Media Access Controller FORMAC Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Implements Media Access Control (MAC) layer protocol for the ANSI X3T9.5 standard (Fiber Distributed Data Interface, FDDI) ■ Error detection capability

Contextual Info: MCC Average Forward Current @ Half-Wave Resistive Load 60Hz > & . Ta O Ir a v i . V o MCC Part Number Maximum Peak Reverse Vottdgt- Forward Peak Surge Current @ 8.3mS Superimposed Maximum Reverse Current @ PRV m 25°C Ta Maximum Forward Voltage @ 25°C TA

fVOA

Contextual Info: s r / C O A X . 2 2 / p l a n s / s . Af t R 2 8 0 2 B 7 1 0 ^ 8 8 7 7 m TECHNICAL COAXIAL department DATA R 280 287 100 8811 MCX issue : FEEDTHROUGH FOR P.C.B SOLDER TYPE SERIES: CABLE .047 .279 Page O 1 / 0 2 DIA .051 0 1.3 (MOUNTING HOLE) N 3 x DIA .043

AN7173K

Abstract: an7173k btl circuit AN7173 an7171 2.1 ch audio amplifiers AN7171NK audio sonic amplifier circuit diagram diagram circuit btl
Contextual Info: ICs for Audio Common Use A N 7171N K , A N 7173K A N 717 1 NK, A N 7173K Dual BTL 14W A udio P ow er A m plifier C ircuits • O u tlin e U nit mir The AN7171NK and th e AN7173K are th e integrated circuits designed for 14W 135V. Ail output power amplifier. Stereoopern

PIC 8 F 77

Abstract: BTZ12 schematic diagram UPS using pic PLC in vhdl code digital clock using logic gates digital clock vhdl code PCI-VME64 IBM vhdl code for D Flipflop synchronous vhdl code for multiplexer 32 to 1 BMS12
Contextual Info: Application Note January 2002 ORCA Series 3 FPGAs Programmable I/O Cell PIC : Logic, Clocking, Routing, and External Device Interface Abstract This application note describes the features and advantages of the ORCA Series 3 FPGA programmable I/O cell (PIC). The Series 3 PIC architecture is

Framatome Connectors

Abstract: CBH2X62SC-V1Z
Contextual Info: NOTES; UNLESS OTHERWISE SPEC fED: -H ACCEPTS ;^ § T H < PCB CATALOG NUMBER DESCRIPTION C B H 2X170S C - V _ CONNECTOR SEM ES CARD EDGE J Z_ Bh-LEVEL CONTACTS I “ DESIGN 1 -2,16 4 -3 ^ 5 9 *2 ,5 4 SEE SHEETS 2 ft 3 FOR RECOMMENDED MATING DAUGHTERCARD AND MOTHERBOARD LAYOUTS.

Am79C82

Abstract: AM79C83GC AM79C83 THT bsc 25 H-14 NP10 xbxr carrier recovery AMD Supernet mach 1 to 5 from amd
Contextual Info: a Preliminary Am79C83 Advanced Micro Devices Fiber Optic Ring Media Access Controller FORMAC DISTINCTIVE CHARACTERISTICS • Implements Media Access Control (MAC) layer protocol for the ANSI X3T9.5 standard (Fiber Distributed Data Interface, FDDI) ■ Error detection capability

PQR168

Abstract: Am79C830A CGX169 4570 pin out diagram LG plc plc lg FDD11994 PQR120 15502C
Contextual Info: AMD a Am 79C830A FORMAC Plus CGX169 169-Lead Pin Grid Array Without H eat Sink measured in inches Physical Dimensions 6-3 i l AMD Am 79C830A FORMAC Plus PQR168 168-Pin Plastic Quad FlatPack (Trimmed and Formed) (measured in inches) TOP VIEW 6-4 The SUPERNET 2 Family for FDD11994 Data Book

29021

Contextual Info: 82505TA MULTIPORT REPEATER CONTROLLER MPR • Complies with IEEE 802.3 CSMA/CD Standard for Repeaters (Std ANSI/IEEE 802.3c-1988) ■ _ Jam Signal Generation ■ 10-Mb/s Operation " Eight-Bit Blinding Timer at End of Transmission ■ Allows Up to Eleven Twisted Pair Ports

Am79C82

Contextual Info: a Preliminary Am79C83 Advanced Micro Devices Fiber Optic Ring Media Access Controller FORMAC DISTINCTIVE CHARACTERISTICS • Implements Media Access Control (MAC) layer protocol for the ANSI X3T9.5 standard (Fiber Distributed Data Interface, FDDI) ■ Error detection capability

Contextual Info: a Advanced Micro Devices Am7985A FDDI ENDEC Data Separator EDS DISTINCTIVE CHARACTERISTICS • 100 Mbps, 125 MBaud serial input ■ Selectable loopback modes ■ Clock recovery ■ Single +5-V supply ■ Meets ANSI X3T9.5 Jitter Requirements GENERAL DESCRIPTION

WKX 62

Abstract: VDRAM z014 NEC MCU VD10 VD11 VD12 ZD10 ZD12 ZD13
Contextual Info: METHEUS OMEGA-MCU MEMORY CONTROL UNIT Features - 16Mhz System Clock - G raphics O perations as fast as 4 Pixels per Clock 64 MPixels - 10 Mpixel average vector draw, 16 Mpixel max. - Patented 'T age M ode Drawing" - Pixel Cache for Block Moves - M ultiple M CU s Cascade up to 32 Bits/Pixel

VCC3 1156 01

Abstract: ulc 2003 VCC3 1156 AM7985 AMD Supernet d0323 PQR168 CGX145 H1093 AM7985AJC
Contextual Info: Cl Advanced Micro Devices Am7985A FDDI ENDEC Data Separator EDS DISTINCTIVE CHARACTERISTICS • 100 Mbps, 125 MBaud serial input ■ Selectable loopback modes ■ Clock recovery ■ Single +5-V supply ■ Meets ANSI X3T9.5 Jitter Requirements GENERAL DESCRIPTION