QL6250 Search Results

QL6250-4PQ208C

Contextual Info: QL6250 Eclipse Data Sheet • • • • • • Combining Performance, Density and Embedded RAM 1.0 Device Highlights Flexible Programmable Logic • .25u, 5 layer metal CMOS process Advanced Clock Network • 9 Global Clock Networks • 2.5 V Vcc, 2.5/3.3 V drive capable I/O

Contextual Info: QL6250E Eclipse-E Data Sheet •••••• FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Nine global clock networks: Flexible Programmable Logic  One dedicated • 0.18 µm six layer metal CMOS process

Contextual Info: QL6250E Eclipse-E Data Sheet •••••• FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Nine global clock networks: Flexible Programmable Logic  One dedicated • 0.18 µm six layer metal CMOS process

QL6250E

Abstract: 110C LVCMOS25 PQ208 PT280 QL6325E OA47 6PS484
Contextual Info: QL6250E Eclipse-E Data Sheet •••••• FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Nine global clock networks: Flexible Programmable Logic  One dedicated • 0.18 µm six layer metal CMOS process

Contextual Info: QL6250 Eclipse Data Sheet • • • • • • Combining Performance, Density and Embedded RAM 1.0 Device Highlights Flexible Programmable Logic • .25u, 5 Layer Metal CMOS Process Advanced Clock Network • 9 Global Clock Networks • 2.5 V Vcc, 2.5/3.3 V Drive Capable I/O

Contextual Info: QL6325E Eclipse-E Data Sheet •••••• FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Nine global clock networks: Flexible Programmable Logic  One dedicated • 0.18 µm six layer metal CMOS process

QL6325E

Abstract: LVCMOS25 QL6250E QL8025 QL8025-7PV100C QL8050 QL8150 QL8250 QL8325 OA47
Contextual Info: Eclipse-II Family Data Sheet • • • • • • Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Multiple dedicated low skew clock networks Flexible Programmable Logic • High drive input-only networks

BS3216

Abstract: 000D PQ208 PT280
Contextual Info: BS3216 Utopia Level 3 to Level 2 Slave Bridge Device Datasheet Version 1.0 - July 2001 Utopia Level 3 to Level 2 Slave/Slave Bridge Datasheet 1 BS3216 Utopia Level 3 to Level 2 Slave Bridge Device Datasheet Version 1.0 - July 2001 CONTENTS 1 INTRODUCTION . 3

T14 N03

Abstract: 000D 001B QL6250 QL6250-PQ208 XENB
Contextual Info: MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 Utopia Level 2 Slave to Utopia Level 1 Master Multiplexer Datasheet 1 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 CONTENTS 1 INTRODUCTION . 3

4032 multiplexer

Contextual Info: Eclipse Family Data Sheet • • • • • • Combining Performance, Density and Embedded RAM 1.0 Device Highlights Flexible Programmable Logic • .25u, 5 layer metal CMOS process Programmable I/O • High performance Enhanced I/O EIO : • 2.5 V Vcc, 2.5/3.3 V drive capable I/O

Contextual Info: QL6325E Eclipse-E Data Sheet •••••• FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Nine global clock networks: Flexible Programmable Logic  One dedicated • 0.18 µm six layer metal CMOS process

Contextual Info: Eclipse II Family Data Sheet • • • • • • Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Multiple dedicated low skew clock networks Flexible Programmable Logic • High drive input-only networks

TFBGA196

Abstract: LVCMOS25 QL6250E QL6325E QL8025 QL8025-7PV100C QL8050 QL8150 QL8250 QL8325
Contextual Info: Eclipse-II Family Data Sheet • • • • • • Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Multiple dedicated low skew clock networks Flexible Programmable Logic • High drive input-only networks

THERMAL Fuse m20

Abstract: QL6600 AA10 QL6250 QL6250-4PQ208C QL6250-4PS484C QL6250-4PT280C QL6325 QL6500 K25 4032
Contextual Info: Eclipse Family Data Sheet •••••• Combining Performance, Density, and Embedded RAM Device Highlights Flexible Programmable Logic • 0.25 µ, 5 layer metal CMOS process Programmable I/O • High performance: <3.2 ns Tco • Programmable slew rate control

BM*228

Abstract: BM2216 000D PQ208 PT280
Contextual Info: BM2216 / BM228 Utopia Level 2 Master Bridge Device Datasheet Version 1.0 - July 2001 Utopia Level 2 Master/Master Bridge Datasheet 1 BM2216 / BM228 Utopia Level 2 Master Bridge Device Datasheet Version 1.0 - July 2001 CONTENTS 1 INTRODUCTION . 3

110C

Abstract: LVCMOS25 QL8025 QL8050 QL8150 QL8250 QL8325 OA47
Contextual Info: Eclipse II Family Data Sheet • • • • • • Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Multiple dedicated low skew clock networks Flexible Programmable Logic • High drive input-only networks

Contextual Info: Eclipse-E Family Data Sheet •••••• FPGA Combining Performance, Density, and Embedded RAM Device Highlights Flexible Programmable Logic • 0.18 µm six layer metal CMOS process • 1.8/2.5/3.3 V drive capable I/O • Up to 1536 logic cells • Up to 4,002 flip-flops

Contextual Info: Eclipse II Family Data Sheet • • • • • • Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Multiple dedicated low skew clock networks Flexible Programmable Logic • High drive input-only networks

RH1034-1.2

Contextual Info: 4/ FOLSVH 'DWD 6KHHW W W W W W W &RPELQLQJ 3HUIRUPDQFH 'HQVLW\ DQG (PEHGGHG 5$0 'HYLFH +LJKOLJKWV OH[LEOH 3URJUDPPDEOH /RJLF ‡ .25 µm, Five layer metal CMOS Process $GYDQFHG &ORFN 1HWZRUN ‡ Nine Global Clock Networks: ‡ One Dedicated ‡ Eight Programmable

Contextual Info: Eclipse II Family Data Sheet • • • • • • Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Multiple dedicated low skew clock networks Flexible Programmable Logic • High drive input-only networks

ACTEL CROSS REFERENCE

Abstract: XC95144 equivalent SX32a OR2C04A epm7064s cross reference epf10k200s Actel A40MX04 2032VE
Contextual Info: Actel Cross Reference Guide Competitor Device Max I/Os Actel Solution Max I/Os Actel Solution Competitor Device XC4000V - 2.5V XC4000E - 5.0V XC4003E Competitor Device 80 Max I/Os Actel Solution Competitor Competitor Device Device Voltage Max Max Flip-flops

BS228

Abstract: 000D BS2216 PQ208 PT280
Contextual Info: BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 Utopia Level 2 Slave/Slave Bridge Datasheet 1 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 CONTENTS 1 INTRODUCTION . 3

PQ208

Abstract: PT280 QL6250 QL6325 QL6500 QL6600 HF 1932
Contextual Info: Eclipse Family Data Sheet • • • • • • Combining Performance, Density, and Embedded RAM Device Highlights Flexible Programmable Logic • 0.25 µ, 5 layer metal CMOS process • 2.5 V Vcc, 2.5/3.3 V drive capable I/O • Up to 4032 logic cells • Up to 583,000 max system gates