PUTS Search Results

Contextual Info: TYPES SN5480, SN7480 GATED FULL ADDERS D E C E M B E R 1972 - logic R E V iS E D D E C E M B E R 1983 S N 5 4 8 0 .J PA CK AG E SNS480 . . . W P A C K A G E SN7480 . . . J O R N P A C K A G E F U N C T IO N T A B L E See Notes 1, 2, and 3 IN PUTS (TOP VIEW)

TDA3664

Abstract: 80C51 82B96 P89LPC925 P89LPC936 TDA3663 PWM generators
Contextual Info: NXP Ultra-high brightness RGBA LED reference design with dimming Inherent system flexibility for solid-state lighting NXP’s ultra-high brightness RGBA LED driving reference design with dimming puts flexible, low-cost systems at your fingertips. It’s a fully tested solution based on robust components

SOP 8 200MIL

Abstract: serial flash 256Mb fast erase spi TM 1628 IC SOP Micron 512MB NOR FLASH HN29V1G91T-30 HN58C1001FPI-15 M5M51008DFP-70HI 256mb EEPROM Memory CSP-48 TSOP 28 SPI memory Package flash
Contextual Info: Renesas Memory General Catalog 2003.11 Renesas Memory General Catalog Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with

Contextual Info: FEATURES • 15 ns MAXIMUM GUARANTEED PROP­ AGATION DELAY • 20 m A MAXIMUM INPUT BIAS CURRENT • TTL COMPATIBLE STROBES AND OUT­ PUTS • OPEN COLLECTOR OUTPUT FOR “WIRE-OR’D” APPLICATIONS • LARGE COMMON MODE INPUT VOLT­ AGE RANGE • OPERATES FROM STANDARD SUPPLY

M74LS640-1P

Abstract: 20P4 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS640-1P OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT INVERTED DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M 74L S 64 0-1P is a semiconductor integrated circuit containing 8 bus transmitters/receivers w ith inverted ou t­ puts. DATA

T54LS183D2

Abstract: wallace-tree
Contextual Info: DUAL CARRY-SAVE FULL ADDER DESCRIPTION The T54LS183/T74LS183 is a Dual Adder charac­ terising high-speed, high-fan-out Darlington out­ puts, all puts are diode clamped for system design simplification. A separate carry output for each bit is designed to be used in multiple intput,

LS298

Abstract: cmos data selector data selector 74HC MC74HCXXXN 74hc298
Contextual Info: g MC54/74HC298 MOTOROLA Product Preview HIGH-PERFORMANCE CMOS LOW-POWER COMPLEMENTARY MOS SILICON-GATE QUAD 2-INPUT DATA SELECTOR/ MULTIPLEXER W ITH OUTPUT LATCH The MC54/74HC298 is identical in pinout to the LS298. The device in­ puts are compatible w ith standard CMOS puts; w ith pullup

WCL 209

Abstract: ltzt
Contextual Info: as DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS114/114A offer common clock and common clear puts and individual J, K, and set puts. These monolithic dual flip-flops are de­ signed so that when the clock goes HIGH, the in­ puts are enabled and data will be accepted. The

HD74LSoop

Abstract: 1S2074 74LSOO HD74LS195A Hitachi Scans-001 Scans-0014928
Contextual Info: H D 74 L S 19 5A . 4-b¡t Parallel-Access Shift Registers This 4-bit register features parallel puts, parallel puts. is loaded into the associated flip-flop and appears at the out­ puts after the positive transition of the clock input. During loading, serial data flow is inhibited. Shifting is accomplished

Contextual Info: 3.3V CMOS HEX INVERTER WITH OPEN-DRAIN OUT­ PUTS, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - IDT74LVC05A ADVANCE INFORMATION 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 1,27mm pitch SOIC, 0.65mm pitch SSOP and

Contextual Info: IDT74LVC623A 3.3V CMOS OCTAL ADVANCE INFORMATION TRANSCEIVER WITH DUAL ENABLE, 3-STATE OUT­ PUTS, 5 VOLT TOLERANT I/O FEATURES: - 0.5 M IC R O N C M O S Technology E S D > 2 0 0 0 V per M IL -S T D -8 8 3 , Method 3 0 15; > 2 0 0 V using m achine model C = 2 0 0 p F , R = 0

Contextual Info: IDT74LVCH162543A 3.3V CMOS 16-BIT ADVANCE REGISTERED TRANSCEIVER INFORMATION WITH 3-STATE PUTS, 5 VOLT TOLERANT I/O, BUS-HOLD flow. The A-to-B enable CEAB must be low in order to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent lowto-high transition of LEAB puts the A latches in the storage

LCX373

Abstract: 74LCX Logic Family Specifications 74LCX373 74LCX373MSA 74LCX373MSAX 74LCX373SJ 74LCX373SJX 74LCX373WM 74LCX373WMX
Contextual Info: LCX373 National é * Semiconductor 74LCX373 Low-Voltage Octal Transparent Latch with 5V Tolerant puts and puts General Description Features The LCX373 consists of eight latches with TRI-STATE out­ puts for bus organized system applications. The device is

T54LS154D2

Contextual Info: PRELIMINARY DATA 4-LINE-T0-16-LINE DECODERS/DEMULTIPLEXERS DESCRIPTION The T54LS/T74LS154 is a 4-line-to-16-line deco­ der. It provided decoding of four binary-coded in­ puts into one of sixteen mutually exclusive puts when both the strobe puts, Ei and E , are in the

74HC181

Abstract: MC74HCXXXN ls181 74HC series j 182 74HC 74HC LOGIC PINOUT
Contextual Info: g M OTOROLA MC54/74HC181 Product P re v ie w HIGH-PERFORMANCE CMOS LOW -POWER CO M PLEM ENTARY MOS S ILICO N-G ATE 4-BIT ARITHMETIC LOGIC UNIT The M C54/74HC181 is identical in p in o u t to the L S I81. The device in­ puts are com p a tib le w ith standard CM OS o puts; w ith pullup

full adder carry look ahead

Abstract: MC5480 MC7480 MMD7000 VIC7480 MC9380
Contextual Info: MTTL Complex Functions MOTOROLA G A T E D FU LL A D D E R M C5480 • M C7480 M C 9 3 8 0 - M C8380 A d d S u ffix S u ffix S u ffix These in puts, The n 0 1 t- F f o r T O - 8 6 c e r a m i c p a c k a g e i C a s t 6 0 •’ . L f o r T O - 1 1 6 c e r a m i c p a c k a g e <C ii s e 6 3 2 .

lm1281n

Abstract: LM1205 LM1208 LM1281 N28B OSD ic national semiconductor 1976
Contextual Info: S e m i c o n d u c t o r LM1281 85 MHz RGB Video Amplifier System with On Screen Display OSD General Description Features The LM1281 is a full feature video amplifier with OSD in­ puts, all within a 28-pin package. This part is intended for use in monitors with resolutions up to 1024 x 768. The video

MA05B

Abstract: NC7LCX00M5 NC7LCX00M5X national semiconductor cmos
Contextual Info: ADVANCE INFORMATION Semiconductor NC7LCX00 Low Voltage Single 2-Input NAND Gate with 5V Tolerant puts General Description Features The LCXOOO contains a single 2-input NAND gate. The in­ puts tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems.

AM685

Abstract: LT685 LT685C LT685CH LT685CJ LT685CN LT685M LT685MH LT685MJ
Contextual Info: rrimm JtkrnmW TECHNOLOGY _LT685 High Speed Comparator F€ATUR€S DCSCRIPTIOd • ■ ■ ■ ■ ■ ■ The LT685 is an ultra-fast comparator with differential in­ puts and complementary puts fully compatible with ECL logic levels. The output current capability is adequate

Contextual Info: June 1989 DM5405/DM7405 Hex Inverters with Open-Collector puts General Description Pull-Up Resistor Equations This device contains six independent gates each of which performs the logic INVERT function. The open-collector out­ puts require external pull-up resistors for proper logical op­

Contextual Info: August 1995 Semiconductor & DM74ALS38A Quadruple 2-lnput NAND Buffer with Open-Collector puts General Description Features This device contains four independent gates, each of which performs the logic NAND function. The open-collector out­ puts require external pull-up resistors for proper logical op­

9602D

Contextual Info: S E M IC O N D U C T O R tm 9602/DM9602 Dual Retriggerable, Resettable One Shots General Description Features These dual resettable, retriggerable one shots have tw o in­ puts per function; one w hich is active high, and one w hich is active low. This allows the d esigner to em ploy either

rtd 2486

Abstract: YM6063 YM6063B TC9200 cdi wiring diagram YAMAHA RA 200 make dc cdi ADPCM NEC yamaha 68000 hr/rtd 2486
Contextual Info: YAMAHA L S I YM6063B CD- I Data Controller CDC • OUTLINE The CDC (CD-I Data Controller) is a data processor capable of handling data from both CD-I and CD-ROM sources. This receives data read out from a CD-I disk and detects the synchronous pattern, then descrambles the data and puts it in a buffer. File and channel

Contextual Info: a WPS256K32-XXC M/HITE /MICROELECTRONICS 256Kx32 SRAM MODULE ADVANCED* FEATURES • Access T im e s * ■ C o m m e rc ia l T e m p e ra tu re R ange B iC M O S : 10ns ■ TTL C o m p a tib le In puts and O u tp u ts ■ 5 V o lt P o w e r S u p p ly ■