PS7084C Search Results

Contextual Info: f j j P ER I COM PI6C5930 Low Skew CMOS PLL Clock Driver Features Description • Wide frequency range: 100 MHz max. The PI6C5930 clock driver uses a PLL phase-locked loop to reduce time skew between a reference clock input (SYNC) and the

Ba 5930

Contextual Info: f¡J PERICOM j J j J 1 11 I 11 j II I I I I I I I I I M I 11 I JI ! I M I M I PI6C5930 I 1 JI 11 I 11 I I J I I I I I I I I I I I I 11 I 11 I 1 1 ] I ! I I I I I I I I I I I J I J I I I I I I I I I I I I I I I 11 I f I I 11 1 I I Low Skew CMOS PLL Clock Driver