PI6C5930 Search Results

Contextual Info: f j j P ER I COM PI6C5930 Low Skew CMOS PLL Clock Driver Features Description • Wide frequency range: 100 MHz max. The PI6C5930 clock driver uses a PLL phase-locked loop to reduce time skew between a reference clock input (SYNC) and the

Contextual Info: PI6C5930

Ba 5930

Contextual Info: f¡J PERICOM j J j J 1 11 I 11 j II I I I I I I I I I M I 11 I JI ! I M I M I PI6C5930 I 1 JI 11 I 11 I I J I I I I I I I I I I I I 11 I 11 I 1 1 ] I ! I I I I I I I I I I I J I J I I I I I I I I I I I I I I I 11 I f I I 11 1 I I Low Skew CMOS PLL Clock Driver

PI6C5930Q

Contextual Info: PI6C5930

Contextual Info: f¡J PER ICOM Features • • • • • • • • • PI6C5930 Mi i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i Low Skew CMOS PLL Clock Driver Description Wide frequency range: lOOMHzmax Five Q and one Q/2 outputs

PI74FCT2841atq

Abstract: PI74FCT191TW PI74FCT2273ATS PI6C2408A-1HL PI74FCT162H245ATV PI3C34X461NB PI5A319AP PI5C3306LE PI74ALVC162835FA PI74FCT153CTW
Contextual Info: Pericom Semiconductor Corp. • 3545 North First St. • San Jose, CA 95134 • USA PRODUCT DISCONTINUANCE NOTIFICATION PDN PDN Number: 04-0601 Issue Date: June 30, 2004 Product(s) Affected: Please see the enclosed Notice Letter Please see the enclosed Product List

Contextual Info: H PERI COM Product F eatures: • • • • • • • • • • ProductDescription: Q/2 output. 5 Q outputs <500 ps output skew, Q4-Q0 Outputs tri-state and reset while OE LOW PLL bypass feature for low frequency testing Internal loop filter RC network

PI6C2501

Abstract: PI6C2509A PI6C5930 SIGNAL PATH DESIGNER
Contextual Info: Application Note 14

PI49FCT3818D

Abstract: P16C2510-133 P16C2510 Pentium 66
Contextual Info: TABLE OF CONTENTS General Information Page Table of C o n ten ts. 3 Introduction. 5

w48c60

Abstract: CDC2510A W48C67-01 w48c67 w48c60-414 W48C60-202 QS53806 IDT49FCT3 W48S67 1CS9159C-14
Contextual Info: fjjPERICO M II I II I I II I I II I II II I II I II II I I I I I II I M I I I I I II I I I I I I I I I II I I I I I II I II I I I I I I M I I M I I I I I I I < I I 1 II I I I I I II I I I I II II I I M I I I II Pericom’s SiliconClock Cross Reference Guide