PS-4480 B Search Results

Contextual Info: Bulletin 12063/A International ^R ectifier SD153N/R SERIES FAST RECOVERY DIODES Stud Version Features • H ig h p o w e r F A S T re c o v e ry d io d e s e r ie s ■ 1 .0 to 1 .5 |js re c o v e ry tim e ■ H ig h v o lta g e ra tin g s up to 1 6 0 0 V

18f2580

Abstract: PIC18F2480 PIC18XXX8 PIC18FX480 HD 4480 PIC18F4480 application example code PIC18F2580 PIC18F4480 PIC18F4580 E11H
Contextual Info: PIC18F2480/2580/4480/4580 Data Sheet 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology 2007 Microchip Technology Inc. Preliminary DS39637C Note the following details of the code protection feature on Microchip devices:

L512F

Abstract: ac202a AZ 280 chip AC-202A on line ups circuit schematic diagram E72445
Contextual Info: I E5HE537 55E » CRYD0 Ï1 co :_— □Ü0D7GÛ _ — , 1 Tb • CRY 'JM fô U W CLÛfôü@@ 0@@ffi)fi^0€/MQ Ki / î ' ' ; ' -, :j . - Series Type L-Case style - Ceramic Bas.e) , Current . 3 -15 Amps 5 - 25 Amps 6 - 42.5 Amps* Example: L512F

Y51 h 85c

Abstract: 4560 opamp 7377 y133 KS0606 Y176 CTR CAPACITOR DATASHEET Y152 Y228 Y239
Contextual Info: 240CH SOURCE DRIVER FOR TFT LCD KS0606 INTRODUCTION KS0606 is 240 output liquid crystal display LCD source driver. It is used in the liquid crystal display panel for pocket sized TV, CNS etc. After sampling and holding at the SAMPLE-HOLD circuit at the clock synchronized timing, the R,G,B, 3CH. video

Contextual Info: • R A dvanced W 'æ APT pow er Te c h n o l o g y ' io o v 10 M 11 JV R i 44 a 0.011 q POWER MOS V‘ Power MOS V is a new generation of high voltage N-Channel enhancement mode power MOSFETs. This new technology minimizes the JFET effect, increases packing density and reduces the on-resistance. Power MOS V®

PAR/2900K

Contextual Info: DATA SHEET CLL042-1218A5-273M1A2 DATA SHEET 1/11 1. Scope of Application This data sheet is applied to the LED package, model CLL042-1218A5-273M1A2. 2. Part code CLL 042 - 12 18 A5 - 27 3 M1 A2 [1] [2] [3] [4] [5] [6] [1] Part Code [2] Dies in series quantity

K4H510438D-ZCB3

Abstract: K4H510438DZCCC tsop-ii 66PIN JEDEC TRAY "Material Declaration Sheet" tsop-ii 66 JEDEC TRAY k4h511638d
Contextual Info: K4H510438D K4H510838D K4H511638D DDR SDRAM 512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

str 4479

Abstract: 3N204 3n206 3N204 equivalent 3N205
Contextual Info: T Y P ES 3N204, 3N205, 3N206 N -C H A N N E L D U A L-G A T E D EP LETIO N -TYP E IN S U LA T E D -G A T E F IE LD -E FF E C T TR A N S IS TO R S B U L L E T IN N O . D L -S 7 2 1 1 7 1 7 , M A Y 1 97 2 D EPLETIO N -TYPE MOS S ILIC O N TRAN SISTO RS • Monolithic Gate-Protection Diodes

HYMD512646A8J

Contextual Info: 128Mx64 bits Unbuffered DDR SDRAM DIMM HYMD512646A8J DESCRIPTION Preliminary Hynix HYMD512646A L 8J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 128Mx64 high-speed memory arrays. Hynix HYMD512646A(L)8J series

1N4475

Abstract: 1N4465 1N4479 1N4466 1N4433 IN47 5C 1N4474 1N4469 1N4535 MIL-S-19500/406
Contextual Info: Zener Voltage 3t Izr @ mA Zener Type No. Volts 1N4418 1N4419 1N4420 39.0 43.0 47.0 1N4421 1N4422 1N4423 1N4424 1N4425 1N4426 51.0 56.0 62.0 Max. Zener Impedance @ Izt Ohms 21.0 23.0 26.0 30.0 33.0 40.0 68.0 75.0 82.0 6.5 6.0 5.5 5.0 4.5 4.0 3.7 3.3 3.0 1N4427

ps5120

Contextual Info: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tuneability in

PS-4480 B

Abstract: E196 MC100 MC100EP196 ps 5040 750MV
Contextual Info: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tuneability in

JBT6K14-AS

Abstract: hvr diodes toshiba 2647 T6K14 VR12 LV 1084 73 Voltage Regulator 7 segment display 10 pin 4026 digital counter
Contextual Info: T6K14 TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T6K14 COLUMN ROW DRIVER LSI FOR DOT MATRIX GRAPHIC LCD The TOSHIBA T6K14 is a driver for a small or medium scale dot matrix graphic LCD, especially for reflecting color STN LCD. This LSI incorporate 65 row output, 128 column output and 65 x

MC100

Abstract: MC100EP196 MC100EP196FA MC100EP196FAR2 Variable Resistor 3305
Contextual Info: MC100EP196 Product Preview 3.3V/5VĄECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar

Contextual Info: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar

Contextual Info: MC100EP196A 3.3 V ECL Programmable Delay Chip With FTUNE The MC100EP196A is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further

Contextual Info: MC100EP196B 3.3 V ECL Programmable Delay Chip With FTUNE Descriptions The MC100EP196B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar

MC100EP195

Abstract: MC100EP195FA MC100EP195FAR2 MC10EP195 MC10EP195FA MC10EP195FAR2 marking EE
Contextual Info: MC10EP195, MC100EP195 3.3V ECL Programmable Delay Chip The MC10/100EP195 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and

S10K625

Abstract: S10K250 S10K275 Siemens varistor
Contextual Info: SIEMENS/ SPCLt SENICONDS ~ aa 0 2 3 bBHD 0 0 1 4 5 2 7 û ~ 7 -c / / - X - / SIOV’s Metal Oxide Varistors for Transient Suppression Features: □ Nanosec. Switching Response Time, < 15 nsec. with minimal lead length. □ HlghTransient Current Capability(up

Contextual Info: MC100EP195B 3.3V ECL Programmable Delay Chip Descriptions The MC100EP195B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and

Contextual Info: MC100EP196B 3.3 V ECL Programmable Delay Chip With FTUNE Descriptions The MC100EP196B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar

Contextual Info: MC100EP195B 3.3V ECL Programmable Delay Chip Descriptions The MC100EP195B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and

2415 9450

Abstract: ic 4440 circuit diagram QFN-32 footprint MC100EP195 MC10EP195 QFN32 LQFP32 footprint
Contextual Info: MC10EP195, MC100EP195 3.3V ECL Programmable Delay Chip The MC10/100EP195 is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. http://onsemi.com

Contextual Info: MC10EP195, MC100EP195 3.3V ECL Programmable Delay Chip The MC10/100EP195 is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. http://onsemi.com