PS-1250 F1 Search Results

panasonic msds

Abstract: 100AH battery charging PS-1250 battery 150 Ah 20HR
Contextual Info: 12 Volt 5.0 AH PS-1250 Features • Absorbent Glass Mat AGM technology for superior performance • Valve regulated, spill proof construction allows safe operation in any position • Power/volume ratio yielding unrivaled energy density • Rugged impact resistant ABS case and cover (UL94-HB)

Contextual Info: « HEX D-LATCH SYNERGY SY100S350 SEMICONDUCTOR DESCRIPTION FEATURES • Max. transparent propagation delay of 900ps ■ Min. Master Reset and Enable pulse widths of 100ps ■ I ee mln. of -98m A ■ ESD protection of 2000V ■ Industry standard 100K ECL levels

5a6v

Abstract: F100K SY100S350 SY100S350DC SY100S350FC SY100S350JC
Contextual Info: * HEX D-LATCH SYNERGY SY100S350 S E M IC O N D U C TO R D E S C R IP T IO N FEATURES • Max. transparent propagation delay of 900ps ■ Min. Master Reset and Enable pulse widths of 100ps ■ I e e mln. of -98m A ■ ESD protection of 2000V ■ Industry standard 100K ECL levels

Contextual Info: S YN ER G Y S E M IC O N D U C T O R F EA TU R E S Max. transparent propagation delay of 900ps Min. Master Reset and Enable pulse widths of lOOps I ee min. of -98mA Industry standard 100K ECL levels Extended supply voltage option: Vee = -4.2V to -5.5V Voltage and temperature compensation for

F100K

Abstract: SY100S350 SY100S350DC
Contextual Info: « SYNERGY H E X D' LATCH SY100S350 S E M IC O N D U C T O R FEATURES DESCRIPTION I Max. transparent propagation delay of 900ps I Min. Master Reset and Enable pulse widths of 100ps I I e e min. of -98mA I ESD protection of 2000V I Industry standard 100K ECL levels

Contextual Info: * HEX D-LATCH SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION Max. transparent propagation delay of 900ps Min. Master Reset and Enable pulse widths of 100ps Ie e SY100S350 min. of -98mA ESD protection of 2000V Industry standard 100K ECL levels Extended supply voltage option:

URD 44 TTF

Abstract: V0063 170M6018 6,6 URD 233 plaf 2000 Abb softstarter ABB soft starter SOLID STATE RELAY TAR DH145 inside delta connection abb dc motor 250v
Contextual Info: Softstarter range Latest updated 00-07-18 Catalogue 1SFC 288001-en, ed5. June 2000 ABB Building Technologies Contents: Description 3 Ordering data PS S 4 Accessories PS S 5 Ordering data PS D 6 Ordering data PS DH 7 General technical data 8 Technical data

Contextual Info: * HEX D-LATCH SYNERGY SY100S350 SEMICONDUCTOR FEATURES DESCRIPTION Max. transparent propagation delay of 900ps Min. Master Reset and Enable pulse widths of 100ps Iee min. o f-98 m A Industry standard 100K ECL levels Extended supply voltage option: V ee = -4.2V to -5.5V

DI 437 EB

Contextual Info: * HEX D-LATCH SYNERGY SY100S350 SEMICONDUCTOR FEATURES DESCRIPTION Max. transparent propagation delay of 900ps Min. Master Reset and Enable pulse widths of 100ps I e e min. o f-9 8m A Industry standard 100K ECL levels Extended supply voltage option: V ee = -4.2V to -5.5V

ETU45B

Abstract: ETU27B ETU76B
Contextual Info: 1 Siemens AG 2015 Air Circuit Breakers 1/2 Introduction 1/9 1/10 1/17 1/24 1/31 1/38 1/45 3WL air circuit breakers/ non-automatic air circuit breakers up to 6300 A AC , IEC Introduction 3-pole, fixed-mounted versions 3-pole, withdrawable versions 4-pole, fixed-mounted versions

Contextual Info: * QUINT AND/NAND GATE SYNERGY SY100S304 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of I050ps Iee min. of -60mA ESD protection of 2000V Extended supply voltage option: — VEE = -4.2V to -5.46V Voltage and temperature compensation for Improved noise Immunity

F100K

Abstract: SY100S350 SY100S350FC SY100S350JC SY100S350JCTR
Contextual Info: HEX D-LATCH FEATURES Q1 Q1 Q0 D0 Q0 VEES PIN CONFIGURATIONS D1 11 10 9 8 7 6 5 D2 Ea 12 13 14 15 16 17 Eb 18 D3 VEE BLOCK DIAGRAM VEES MR D1 D0 R D2 24 23 22 21 20 19 18 D1 2 3 17 16 D0 Q0 15 14 Q0 Q1 13 7 8 9 10 11 12 Q1 Q4 4 5 Q4 6 Top View Flatpack F24-1

hex latch

Abstract: F100K SY100S350 SY100S350FC SY100S350JC SY100S350JCTR
Contextual Info: SY100S350 FINAL HEX D-LATCH FEATURES Q1 Q1 Q0 D0 Q0 VEES PIN CONFIGURATIONS D1 11 10 9 8 7 6 5 D2 Ea 12 13 14 15 16 17 Eb 18 D3 VEE BLOCK DIAGRAM VEES MR D1 D0 R D2 24 23 22 21 20 19 18 D1 2 3 17 16 D0 Q0 15 14 Q0 Q1 13 7 8 9 10 11 12 Q1 Q4 4 5 Q4 6 Top View

Contextual Info: * QUINT AND/NAND GATE SYNERGY SY100S304 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 1050ps The SY100S 304 is an ultra-fast quint AN D /N AN D gate designed for use in high-perform ance ECL system s. This device also fe a ture s a Function F output which is the w ireNOR of the AND gate outputs. T he inputs on the device

Contextual Info: <o> ai 1m CmC i m w lC m m m •v i 00 S 304 “-.j U I N î AimD' N A N D i j A î E ^JSS W S E M /C O N D U C T O P m ssM FEA TU R E S The SY100S304 is an ultra-fast quint AND/NAND gate designed for use in high-performance ECL systems. This device also features a Function F output which is the wireNOR of the AND gate outputs. The inputs on the device

F100K

Abstract: SY100S304 SY100S304DC SY100S304FC SY100S304JC
Contextual Info: * S Y N E R G Y q u in t a n d /n a n d g a t e sy-io o s304 S E M IC O N D U C T O R FEATURES DESCRIPTION I Max. propagation delay of 1050ps I I e e min. o f-60m A The SY 100S 304 is an ultra-fast quint AN D /N AN D gate designed fo r use in high-perform ance ECL system s. This

d 1878 DATA SHEET

Abstract: SN28837 TL1051 TL1593 Diode GP 622 SN28838 SN28846 TC277 TMS3473B GP 624
Contextual Info: SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 description The SN28837 is a monolithic integrated circuit designed to supply timing signals for the Texas Instruments 8-mm-diagonal TC276 PAL color and TC277 (PAL monochrome) CCD image sensors. The SN28837 supplies both CCD-drive

SN28837

Abstract: TL1051 TC276 TL1593 SN28838 SN28846 TC277 TMS3473B TMS34
Contextual Info: SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 description The SN28837 is a monolithic integrated circuit designed to supply timing signals for the Texas Instruments TI 8-mm-diagonal TC276 (PAL color) and TC277 (PAL monochrome) CCD image sensors. The SN28837 supplies both CCD-drive

FR1000BW

Abstract: RCR150BY FR1000BX RCR150BX 1S80 FR150DX FR150DY FR300DX FR300DY FR500AX
Contextual Info: POUEREX INC T1D D • 7 5 T 4 tiS l D D D lf l n 2 ■ Reverse Conducting Thyristors IT W to JW T c -6 5 °C Note 2 (Am ps) I tsm/I rsm (Am ps x 10*) SO Hz 60 Hz lT‘ t/lmt @ & 3 ms (4>sec x Toy iDfíM @ TJ{Utic) VDRM(Mli) (mA) (Note 1) Verna Range (Volts)

2.45 GHz single chip transmitter

Abstract: serdes transceiver 1999 ps-1250 f1
Contextual Info: Gigabit Ethernet SerDes Circuit with Differential PECL Clock Inputs HDMP-1637A SerDes Features • IEEE 802.3z Gigabit Ethernet Compatible, Supports 1250 MBd Gigabit Ethernet • Based on X3T11 “10 Bit Specification” • Low Power Consumption • 10 mm 64-pin PQFP Package

Contextual Info: Whpl HEW LETT mLUMPACKARD Gigabit Ethernet SerDes Circuit w ith Differential PE CL Clock Inputs HDMP-1637A SerDes Features • IEEE 802.3z Gigabit Ethernet Compatible, Supports 1250 MBd Gigabit Ethernet • Based on X3T11 “10 Bit Specification” • Low Power Consumption

HDMP-1637A

Contextual Info: Gigabit Ethernet SerDes Circuit with Differential PECL Clock Inputs HDMP-1637A SerDes Features • IEEE 802.3z Gigabit Ethernet Compatible, Supports 1250 MBd Gigabit Ethernet • Based on X3T11 “10 Bit Specification” • Low Power Consumption • 10 mm 64-pin PQFP Package

7476m

Abstract: TS13 la 6500
Contextual Info: Phase Control Thyristors Type V 2> V D RM V rrm V ii2dt It s m A A2s KA =V T y | max rrm A V/kA T v j max T vj max It a v m V TO V A/°C 180°el sin Tv¡ = Tc = 85°C Tvj max h m£î T vj = T v j max ,103 +100V(50V) up to 1000V T 210 N T 348 N T 398 N T 568 N

Contextual Info: « SYNERGY HEX D-LATCH SY100S350 SEMICONDUCTOR FEATURES • Max. transparent propagation delay of 900ps ■ Min. Master Reset and Enable pulse widths of 100ps ■ Ie e min. of -98m A ■ Industry standard 100K ECL levels ■ Extended supply voltage option: