PROTOCOL Search Results

P686

Contextual Info: TOSHIBA 1. TMP68652 INTRODUCTION The TM P68652 MPCC form ats, tran sm its, and receives synchronous se ria l d ata while supporting bit-oriented protocols BOP or byte-control protocols (BC P). The p a r a lle l b u s of the M PCC re a d ily in te r fa c e s w ith th e 6 8 0 0 an d T L C S -6 8 0 0 0

Contextual Info: DS125DF111 www.ti.com SNLS450 – JANUARY 2014 DS125DF111 Multi-Protocol 2-Channel 9.8 - 12.5 Gb/s Retimer Check for Samples: DS125DF111 FEATURES DESCRIPTION • The DS125DF111 is a dual channel 1-lane bidirectional retimer with integrated signal conditioning. The DS125DF111 includes an input

Contextual Info: ISO-CMOS ST-BUS FAMILY MITEL* HDLC Protocol Controller Features • MT8952B _ ISSUE 5_May 1995 Formats data as per X.25 CCITT level-2 standards Ordering Information MT8952BC 28 Pin Ceramic DIP MT8952BE 28 Pin Plastic DIP

SP508ECF-L

Abstract: 124 resistor SP508EEF-L
Contextual Info: SP508E Rugged 20Mbps, 8 Channel Multi-Protocol Transceiver with Programmable DCE/DTE and Termination Resistors FEATURES Now Available in Lead Free Packaging • 20Mbps Differential Transmission Rates Refer to page 7 for pinout • 15kV ESD Tolerance for Analog I/Os

INF-8074

Contextual Info: AFBR-57J9AMZ Digital Diagnostic SFP, 850nm 6.144 Gb/s, RoHS OBSAI/CPRI Compatible Optical Transceiver Data Sheet Description Features Avago’s AFBR-57J9AMZ optical transceiver supports high speed serial links over multimode optical fiber at signaling rates up to 7.4 Gb/s for wireless base station applications involving the OBSAI or CPRI protocols, as well

NS1000 n

Abstract: S7600A S-7600
Contextual Info: S-7600A TCP/IP NETWORK PROTOCOL STACK LSI Preliminary - Revision 0.11 Functional Specification Preliminary S-7600A TCP/IP Network Protocol LSI Components Marketing Dept. Marketing Section 2 Tel +81-43-211-1028 Fax +81-43-211-8035 8,Nakase 1-chome, Mihama-ku

MPR121

Abstract: AN3895 I2C protocol
Contextual Info: Freescale Semiconductor Application Note AN3895 Rev 1, 03/2010 MPR121 Serial Communication INTRODUCTION The MPR121 uses an I2C Serial Interface. The I2C protocol implementation and the specifics of communicating with the Touch Sensor Controller are detailed in this application note.

TCO-2112

Abstract: AD9516
Contextual Info: 14-Output Clock Generator AD9516-5 FEATURES APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers

interface CC2540

Abstract: SWRS084 circuit diagram of 8051 bus system using zigbee T0436 CC2540 CC2540F128RHAT CC2540F128RHAR 32.768khz crystal microcontroller 8051 application audio sampling c heart rate monitor using microcontroller 8051
Contextual Info: CC2540F128, CC2540F256 www.ti.com SWRS084 – OCTOBER 2010 2.4-GHz Bluetooth low energy System-on-Chip Check for Samples: CC2540F128, CC2540F256 FEATURES • • True Single-Chip BLE Solution: CC2540 Can Run Both Application and BLE Protocol Stack, Includes Peripherals to Interface With Wide

ADSST-1803

Abstract: ADSST modem conexant analog daa microcontroller based caller id RJ11 to RS232 ttl V.34 Modem ADSST-1804 RJ-11 to DB9 telindus digital modem v.92 v.90
Contextual Info: Standalone Embedded Modems COMPLETELY INTEGRATED STANDALONE V.32/V.34/V.90 ATS MODEM CHIPSETS AND CODE • Modem Error Correction and Compression Layer 2 Protocols can Execute on DSP or on Microcontroller. HIGHLIGHTS • Complete Solution Includes DSP, DAA and Modem

24LC16

Abstract: AM24LC02 AM24LC04 AM24LC08 AM24LC16 AM24LC16I AM24LC16V
Contextual Info: ATC AM24LC16 2-Wire Serial 16K-bits 2048 x 8 CMOS Electrically Erasable PROM General Description Features • State- of- the- Art Architecture - Non-volatile data storage - Full range Vcc = 2.7V to 5.5V • 2 wire I2C serial interface - Provides bi-directional data transfer protocol

ntc thermistor k22

Abstract: ntc k25 ILS6261 ntc r54 isl6261 NTC resistor T5 ISL6261CRZ ntc 33 1114 NTC resistor T24 ntc k23 thermistor
Contextual Info: ISL6261 Data Sheet Single-Phase Core Regulator for IMVP-6® Mobile CPUs The ISL6261 is a single-phase buck regulator implementing lntel® IMVP-6® protocol, with embedded gate drivers. September 27, 2006 FN9251.1 Features • Precision single-phase CORE voltage regulator

TJA1054A

Abstract: PCA82C252 PCA82C252T TJA1053 TJA1053T TJA1054 TJA1054AT TJA1054AU TJA1054T CAN-H11
Contextual Info: TJA1054A Fault-tolerant CAN transceiver Rev. 04 — 2 January 2007 Product data sheet 1. General description The TJA1054A is the interface between the protocol controller and the physical bus wires in a Controller Area Network CAN . It is primarily intended for low-speed applications up

7655a

Abstract: CD2481 CL-CD2231 CL-CD2401 CL-CD2431 CL-CD2481 3C3EW CD240 BW-190
Contextual Info: CL-CD2481 Data Book FEATURES • Four full-duplex multi-protocol channels, each running up to 230.4 kbps with 60-MHz clock Programmable Four-Channel ■ Microcode downloadable to on-chip storage supports various asynchronous and synchronous protocols on

PH2401

Abstract: Bluetooth Module adc DS5630 MT1020A 16 bit linear PCM bluetooth transmitter circuit diagram
Contextual Info: MT1020A Bluetooth Baseband Controller Preliminary Information DS5630 Issue 1.8 November 2000 Features Ordering Information ● ● ● ● ● ● ● ● ● ● Bluetooth™ v1.0 Compliant Link Controller Full Bluetooth Protocol Stack up to HCI USB and UART Host Interfaces

JESD22-A114A

Abstract: M34F04
Contextual Info: M34F04 4Kbit Serial I²C Bus EEPROM With Hardware Write Control on Top Half of Memory PRELIMINARY DATA FEATURES SUMMARY 2 • Two Wire I C Serial Interface Supports 400 kHz Protocol ■ 2.5 to 5.5V Single Supply Voltage: ■ Hardware Write Control of the top half of

ATC 24LC02

Abstract: 24lc02 datasheet 24LC02 AM24LC02 AM24LC04 AM24LC08 AM24LC16
Contextual Info: ATC AM24LC02 2-Wire Serial 2K-bits 256 x 8 CMOS Electrically Erasable PROM General Description Features • State- of- the- art architecture - Non-volatile data storage - Supply voltage range: 2.7V ~ 5.5V • 2 wire I2C serial interface - Providing bi-directional data transfer protocol

X24C01

Abstract: X24C16
Contextual Info: X24C01 1K 128 x 8 Bit Serial E2PROM DESCRIPTION • 2.7V to 5.5V Power Supply • Low Power CMOS —Active current less than 1 mA —Standby current less than 50 µA • Internally Organized 128 x 8 • 2 Wire Serial Interface —Bidirectional data transfer protocol

USR24

Abstract: ssi protocol 73D2248
Contextual Info: SSI 73D2248/2348 & MNP5, V.42bis Datacom Modem Device Set i k m M s l m s ' A TDK Group/Company Advance Information January 1993 FEATURES DESCRIPTION The SSI 73D2248/2348 Chip Sets consists of two CMOS integrated circuits which provide the data pump and protocol functions required to implement a high

SiS5511

Abstract: AT6660
Contextual Info: SÌS5511 PCI/ISA Cache Memory Controller 2. SÎS5511 2.1 Features • S upports Intel Pentium CPU and o th er com patible CPU at 66/60/50M Hz external clock speed • Supports Slice M P Protocol • Supports the Pipelined A ddress M ode of P entium CPU.

6 pins IC cbe

Abstract: irca
Contextual Info: S VlïlBl OS D a ta S h eet SYMI3FW600 PCI to IEEE-1394 Host Bus Interface T he SYM13FW600 chip uses the Link Layer protocol o f the IEEE-1394 serial bus. It also provides direct m em o ry access DM A engines for h igh-perform ance data transfer an d a P eripheral

1553 bus

Abstract: HM-65664 80C31M
Contextual Info: 5öbß45b QÜ0E3M3 1ÖT • MMHS January 1991 Preview MATRA H H S 29C530 HI-REL DATA SHEET MIL-STD-1553B PROTOCOL MANAGEMENT UNIT FEATURES . PIN PROGRAMMABLE FEATURES : - COMPATIBILITY WITH INTEL AND MOTOROLA MICROPROCESSORS - 8 OR 16 BIT INTERFACE - SUPPORT OF THREE MEMORY INTERFACE

D15D7

Contextual Info: FUNCTIONAL DESCRIPTION CARNET uses five types of messages with the ARCNET protocol. ITT Token ALERT DID EOT DID FBE (Free Buffer Enquiry) ALERT DID ENQ DID A C K (Acknowledge) ALERT ACK N AK (NACK) ALERT NACK PACKET (Data Packet) The CARNET assigns the first data byte lor Packet ID and sequence number.

IS24C16A-2ZLI

Abstract: IS24C02A-2SLI IS24C02A IS24C04A IS24C08A IS24C16A IS24C04A2GLI IS24C02A-2GLI IS24C04A-2GLI
Contextual Info: IS24C02A IS24C04A IS24C08A IS24C16A ISSI 1K-bit/2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROM MARCH 2005 FEATURES DESCRIPTION • Two-Wire Serial Interface, I2CTM Compatible –Bi-directional data transfer protocol • 400 KHz 2.5V and 1 MHz (5.0V) Compatible