PMD22 Search Results

ADSP-2100

Abstract: PROM BURNER ADDS-2110 dma13 ADSP-2100A ADSP-2100AJG ADSP-2100AKG ADSP-2100JG ADSP-2100JP ADSP-2100KG
Contextual Info: ANALOG DEVICES FEATURES Pin- and Code-Com patible DSP Microprocessors ADSP-2100, 6.144M Hz and 8.192M Hz ADSP-2100A, 10.24M Hz and 12.5MHz Separate Program and Data Buses, Extended Off-Chip Single-Cycle Direct Access to 16K x 16 of Data M em ory Single-Cycle Direct Access to 32K x 24 of Program

Contextual Info: The program memory PMD, PMA buses and data memory (DMA, DMD) buses extend off-chip to provide direct connections to external memories. The DMD bus is the primary bus for routing data internally and to/from external data memory. The 14-bit DMA bus provides direct addressing of 16K x 16 of external

DM024

Contextual Info: ANALOG DEVICES 32/40-Bit IEEE Floating-Point DSP Microprocessor □ ADSP-21020 1.1 Scope. This specification covers the detail requirements for a monolithic CMOS 32/40-bit floating-point DSP microprocessor. 1.2 Part Number. The complete pan number per Table 1 of this specification is as follows:

Contextual Info: 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 ANALOG DEVICES FUNCTIONAL BLOCK DIAGRAM FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maxim izes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle

ADSP-21xxx

Abstract: dmd20 ic tms 1000 ADSP-21XXX MEMORY ADSP-2100 ADSP-21000 ADSP-21020 TSC21020F 21020F
Contextual Info: TSC21020F Radiation Tolerant 32/40–Bit IEEE Floating–Point DSP Microprocessor Introduction Atmel is manufacturing a radiation tolerant version of the Analog Devices ADSP–21020 32/40–Bit Floating–Point DSP. The product is pin and code compatible with ADI

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Abstract: TSC21020E
Contextual Info: TSC21020E Radiation Tolerant 32/40–Bit IEEE Floating–Point DSP Microprocessor Introduction TEMIC Semiconductors is manufacturing a radiation tolerant version of the Analog Devices ADSP–21020 32/40–Bit Floating–Point DSP. The product is pin and code compatible with ADI

PMD4m

Abstract: pmd23 A0335 G03327 ADSP-21020 ADSP-2100 ADSP-21000 TSW161 PMD24 PMD32
Contextual Info: . ANALOG DEVICES INC OßlbBOO 0033252 5 I ¡ANA 4LE ]> -r-V9-/z-û<? IEEE Floating-Point DSP Microprocessor ANALOG DEVICES FUNCTIONAL BLOCK DIAGRAM FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance

2388 84 JRC

Abstract: jrc 2388 yx 8018 tdc1008 ADSP-1080 0620 jrc gsp3f Analog Devices Data-Acquisition Databook 1984 ADSP1080 JRC 2388 84
Contextual Info: DSP PRODUCTS DATABOOK DSP MICROPROCESSORS MICROCODED SUPPORT COMPONENTS FLOATING POINT COMPONENTS FIXED POINT COMPONENTS How to Find Product Data in This Databook T H IS V O LU M E Contains Data Sheets, Selection Guides, Application N otes, and a wealth of background inform ation on com ponents for num ber

ADSP21020BG120

Abstract: ADSP-21020
Contextual Info: BACK a FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle Execution 100 MFLOPS Peak, 66 MFLOPS Sustained Performance 1024-Point Complex FFT Benchmark: 0.58 ms

ADSP-21xxx

Abstract: 21020F ADSP-2100 ADSP-21000 ADSP-21020 TSC21020F
Contextual Info: TSC21020F Radiation Tolerant 32/40–Bit IEEE Floating–Point DSP Microprocessor Introduction TEMIC Semiconductors is manufacturing a radiation tolerant version of the Analog Devices ADSP–21020 32/40–Bit Floating–Point DSP. The product is pin and code compatible with ADI

ADSP-21010

Abstract: ADSp21010 MRF 277 DMD29
Contextual Info: ANALOG DEVICES FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 80 ns, 12.5 MIPS Instruction Rate, Single-Cycle Execution 37.5 MFLOPS Peak, 25 MFLOPS Sustained Performance 1024-Point Complex FFT Benchmark: 1.54 ms

tsc21020f-20sbsv

Abstract: QML-38535 TSC21020F-20MBMQ
Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED A Made technical change in paragraph 1.3. Update boilerplate to MIL-PRF-38535 requirements. - LTG 02-05-29 Thomas M. Hess B Made technical changes in section 1.3 and table I. Add vendor CAGE F7400. Update boilerplate to MIL-PRF-38535 requirements. - LTG

ADSP-21xxx

Abstract: mrf 212 PGA223 ADSP-21000 ADSP21020 ADSP-21020 TSC21020F DMD30
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • • • Superscalar IEEE Floating-Point-Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 50 ns, 20 MIPS Instruction Rate, Single Cycle Execution

ADSP-2100

Abstract: ADSP-2100A ADSP-2100JG ADSP-2100KG DMD15 T145 xmxx ADSP-2100SZ
Contextual Info: ANALOG DEVICES INC IbE D • OfilbflQO 001=1438 4 tl T - W r e a n a lo g L J D EV IC ES | ‘ - r M i o 12.5 MIPS DSP Microprocessor ' FEATURES Pin- and Code-Compatible DSP Microprocessors ADSP-2100, 6.144MHz and 8.192MHz ADSP-2100A, 10.24MHz and 12.5MHz

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Abstract: MRF high power transistor TSC21020E 32 TSC21020E ADSP-21xxx dmd 20 mrf 212 High frequency MRF transistor MRF 238 mrf 245
Contextual Info: TSC21020E Radiation Tolerant 32/40–Bit IEEE Floating–Point DSP Microprocessor Introduction TEMIC Semiconductors is manufacturing a radiation tolerant version of the Analog Devices ADSP–21020 32/40–Bit Floating–Point DSP. The product is pin and code compatible with ADI

Contextual Info: ANALOG DEVICES INC bSE D ö l b ö D G 0D30fl7a TT1 D 32-Bit IEEE Floating-Point DSP Microprocessor ANALOG ► DEVICES FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 80 ns, 12.5 MIPS Instruction Rate, Single-Cycle

ADSP-21xxx

Abstract: ADSP-21000 ADSP21020 ADSP-21020 TSC21020F
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • • Superscalar IEEE Floating-Point-Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 50 ns, 20 MIPS Instruction Rate, Single Cycle Execution

ADSP-21xxx

Abstract: ADSP-21000 ADSP21020 ADSP-21020 TSC21020F
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • • Superscalar IEEE Floating-Point-Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 50 ns, 20 MIPS Instruction Rate, Single Cycle Execution

DMD29

Contextual Info: SPECIFICATION MHS / SCC040 Issue 2B February 2000 Page 1 of 51 PROJET SPACE GENERAL TITLE CMOS MONOLITHIC RADIATION TOLERANT 32/40-BIT IEEE FLOATING-POINT DSP MICROPROCESSOR SPECIFICATION MHS / SCC040 Issue 2B February 2000 Page 2 of 51 DOCUMENTATION CHANGE NOTICE

DM 024

Contextual Info: Temic TSC21020F S e m i c o n d u c t o r s Radiation Tolerant 32/40-Bit IEEE Floating-Point DSP Microprocessor Introduction TEMIC Semiconductors is manufacturing a radiation tolerant version of the Analog Devices A D SP-21020 32/40-B it Floating-Point DSP.

2100SG

Abstract: FIND xo 405 mf xmxx xo 405 mf J3028 PMD230
Contextual Info: ANALOG DEVICES FEATURES Pin- and Code-Compatible DSP Microprocessors ADSP-2100, 6.144MHz and 8.192MHz ADSP-2100A, 10.24MHz and 12.5MHz Separate Program and Data Buses, Extended Off-Chip Single-Cycle Direct Access to 16Kx 16 of Data Memory Single-Cycle Direct Access to 32K x 24 of Program

Contextual Info: • OAlbflOO ANALOG DEVICES PQ4Qfib4 Tfl7 HANA 12.5 MIPS DSP Microprocessor ADSP-2100/ADSP-2100A 1.1 Scope. AN AL OG D E V I C E S INC bSE Js This specification covers the detail requirements for a monolithic CMOS 16-bit fixed-point DSP microprocessor. 1.2 P art N u m b er.

ADSP-21000

Abstract: ADSP21020 ADSP-21020 TSC21020F M 9512 FY MQFPF-256 951200201
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • • • Superscalar IEEE Floating-Point-Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 50 ns, 20 MIPS Instruction Rate, Single Cycle Execution

4153E

Abstract: ADSP-21xxx 5962-9953901VXC TSC21020F DMD20 PMD39 mrf 174 mrf 212 ADSP-21000 ADSP21020
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • • Superscalar IEEE Floating-Point-Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 50 ns, 20 MIPS Instruction Rate, Single Cycle Execution