PLU PROCESSOR Search Results

rt6164

Abstract: 1PXF transformer
Contextual Info: XR-T61 66 C'EXAR [.the a n a lo g plu s Codirectional Digital Data Processor com pan y J M June 1997-3 APPLICATIONS FEATURES • Low Power CMOS Technology • • All Receiver and Transmitter Inputs and Outputs are TTL Compatible CCITT G.703 Interface •

July 2008 QwikConnect

Abstract: July 2008 MS3443H MS3143H Qwik Connect rockwell collins connector M85528/1
Contextual Info: Qwik Connect GLENAIR n JULY 2008 n VOLUME 12 n NUMBER Series 79 MicroCrimp Connectors Crimp Contact Convenience in a Micro-D Shell . . . s Plu The Evolution of Aerospace Quality Assurance Systems 3 QwikConnect Crimp-and-Poke Comes to the MIL-DTL-83513 Micro-D Connector

Contextual Info: PLUTO MITEL Dual Mode CDMA/AMPS Baseband Interface SEMICONDUCTOR A dvance Inform ation D S 4 7 2 2 - 1.8 July 1998 T he PLU TO ba seb an d interface circu it is d e sig ned fo r use in dual m ode C D M A /A M P S digital ce llu la r tele ph on es. In the

aop 741

Abstract: 74s281 SBP0400 SBP0400AC Counters NE 215 ivo MUX ADR 622 SBP0400A 74S482 IC cd 4093 IC Plus
Contextual Info: IN T R O D U C T IO N 1. The S B P 0 4 0 0 A a nd S B P 0 4 0 1 A are 4 -b it e xpandable para lle l b in a ry processor elem ents, each m o n o lith ic a lly in te g ra tin g 1 6 6 0 fu n c tio n a l gates. These c o n tro lle r/p ro c e s s o r b u ild in g blo cks c o m b in e th e u n iq u e p ro p e rtie s o f

SPRS030

Abstract: 224K-word XDS510PP dsp processor Architecture of TMS320C5X
Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C – JULY 1996 – REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

PLE3-12 EP1810

Contextual Info: ÆoniM Glossary June 1996 A Altera Hardware Description Language AHDL A ltera's design entry language. AHDL is a highlevel, modular language that is com pletely integrated into M A X +P L U SII. You can create AHDL Text Design Files (.tdf) with the M A X+PLUS II Text Editor or any standard text

programmer EPLD

Abstract: EPM5000-series EPM5000 EPS464-25 AC01 EPS464-20 logicaps EPM500 waveform-generation
Contextual Info: EPS464 Synchronous Timing Generator EPLD Data Sheet April 1991, ver. 1 F g g tlir & S ^ □ □ □ □ □ □ □ □ H igh-perform ance Synchronous Tim ing Generator STG EPLD ideal for custom w aveform generation and state m achine designs Generates com plex control timing w aveform s for im aging an d display

Contextual Info: EPS464 Synchronous Timing Generator EPLD Data Sheet April 1991, ver. 1 Features ^ □ □ □ □ □ □ □ □ H igh-perform ance Synchronous Tim ing Generator STG EPLD ideal for custom w aveform generation and state m achine designs Generates com plex control timing w aveform s for im aging and display

am2506

Abstract: 74182 carry look-ahead AM250659C 74182 74182 pin diagram 1N3064
Contextual Info: Am2506 Four-Bit Arithmetic Logic Unit/Function Generator with Output Latch Distinctive Characteristics: • P rovides 16 arithm etic operations including add, subtract, double and compare. • Provides ALL 16 possible logic operations of two variables in typically 22 ns.

AS15 G

Abstract: AS15 f as15 h AS15 U as15- f basic block diagram of bit slice processors 9s complement circuit as15 M10800 MC10803
Contextual Info: g MOTOROLA MECL— LSI 4 -B IT ALU SLICE IN TR O D U C TIO N T he M C 108 00 4 - B it A L U S lice is an LSI b u ild in g b lo c k f o r d ig ita l processors. This c ir c u it p e rfo rm s th e necessary lo g ic and a rith m e tic fu n c tio n s re q u ire d to e xecu te th e variou s m a c h in e in s tru c tio n s . Each

TMS320C50DU

Abstract: Acc 2089 mc 4069 TEXAS INSTRUMENTS, die attach datasheet and application 7217 SMJ320C50 SMJ320C50KGD
Contextual Info: SMJ320C50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS007B – JUNE 1996 – REVISED JUNE 2000 D D D D D D D D Processed to MIL-PRF-38535 Fast Instruction Cycle Time of 30 ns and 40 ns Source-Code Compatible With all ’C1x and ’C2x Devices RAM-Based Operation

96708

Abstract: 2128-3 RAM SMJ320C50 SMJ320C50KGD TMS320C50BS diemat 41266 ram
Contextual Info: SMJ320C50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS007A – JUNE 1996 – REVISED JUNE 1997 D D D D D D D Processed to MIL-PRF-38535 Fast Instruction Cycle Time of 30 ns, 40 ns, and 50 ns Source-Code Compatible With all ’C1x and ’C2x Devices RAM-Based Operation

c flex 700

Abstract: excalibur APEX development board nios apex ep20k400 sopc development board nios development kit cyclone edition EPXA-DEVKIT-XA10D EP20K30E EP20K60E excalibur Board EPF10K50S EPXA10-DEV-BOARD
Contextual Info: Design Software & Development Kit Selector Guide January 2003 Introduction SOPC Builder As FPGAs evolve to include system-level building blocks within the device—such as high-speed I/O circuitry, multi-gigabit transceivers, embedded processors, digital signal processing

Acc 2089

Abstract: TMP320C50KGD TMP320LC50KGD 446526 Texas instruments military products
Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C – JULY 1996 – REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

TMP320C50KGD

Abstract: TMP320LC50KGD 8405
Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008B – JULY 1996 – REVISED JUNE 1999 D D D D D D D 35-ns and 50-ns Single-Cycle Instruction Execution Time for 5 V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3 V Operation

Contextual Info: SMJ320C50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS007A - JUNE 1996 - REVISED JUNE 1997 Processed to MIL-PRF-38535 Fast Instruction Cycle Time of 30 ns, 40 ns, and 50 ns Source-Code Compatible With all ’C1x and ’C2x Devices RAM-Based Operation - 9K-Words x 16-Bit Dual-Access On-Chip

Contextual Info: Configuration EPROMs for FLEX Devices Features ^ ^ M ^ m 88 Altera Corporation A -DS-EFROM -Û9 Serial EPRO M fam ily for configuring FLEX devices Easy-to-use 4-pin interface to FLEX devices Low current during configuration and near-zero standby current

TC800CPL

Abstract: tc800 com2502 T511 012 6522 versatile interface adapter t577 O17B
Contextual Info: TELEDYNE COMPONENTS 3bE D m im?h02 00D?lhh 1 • TSC '- « 5 H 0 - 3 0 WTELEDYNE COMPONENTS TC800 15-BIT PLUS SIGN, INTEGRATING ANALOG-TO-DIGITAL CONVERTER FEATURES ■ ■ ■ ■ ■ Easy Conversion Cycle Monitoring and Control — Data Valid Output Signal

cy7c345

Abstract: 7C340 Signal Path Designer IC TTL 7400 free
Contextual Info: PRELIMINARY M CYPRESS SEMICONDUCTOR CY7C340 EPLD Family Multiple Array M atrix High Density EPLDs Features General Description • Erasable, user-configurable CMOS EPLDs capable of implementing high density custom logic functions T h e Cypress M ultiple A rray M a trix

PLDS-MAX

Abstract: Altera Classic EPLDs Altera LP5 ALTERA MAX 5000 programming ALTERA MAX 5000 eps448 logicaps sam plus mpm5192 PLDS-ENCORE
Contextual Info: Index September 1991 A+PLUS design entry 301 design processing 303 EPLD programming 304 functional simulation 304 o verview 299 ABEL2MAX Converter 356 adapters sff P L E D /J /G /S /Q & P L M D /J /G /S /Q adapters ADP (see Altera Design Processor) AHDL (s«1 Altera Hardware Description Language)

Acc 2089

Abstract: datasheet and application 7217 SMJ320C50 SMJ320C50KGD
Contextual Info: SMJ320C50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS007B − JUNE 1996 − REVISED JUNE 2000 D Processed to MIL-PRF-38535 D Fast Instruction Cycle Time of 30 ns and 40 ns D Source-Code Compatible With all ’C1x and D D D D D ’C2x Devices RAM-Based Operation

7404

Contextual Info: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C – JULY 1996 – REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation

7217

Abstract: Acc 2089 SMJ320C50 SMJ320C50KGD TMS320C50DU
Contextual Info: SMJ320C50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS007B – JUNE 1996 – REVISED JUNE 2000 D D D D D D D D Processed to MIL-PRF-38535 Fast Instruction Cycle Time of 30 ns and 40 ns Source-Code Compatible With all ’C1x and ’C2x Devices RAM-Based Operation

counter 7468

Abstract: 74565 MIL I 23659 6884 TMP320C50KGD 68840
Contextual Info: TMP320C50KGD, TMP320BC51KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008A – JULY 1996 – REVISED JUNE 1997 D D D D D D Fast Instruction Cycle Times of 35 ns and 50 ns Source-Code Compatible With all ’C1x and ’C2x Devices RAM-Based Operation – 9K-Words x 16-Bit Dual-Access On-Chip