PLLS Search Results

F1523BA

Abstract: F1523BAM
Contextual Info: VOLTAGE CONTROLLED CRYSTAL OSCILLATOR F1523BA The Fox F1523BA is a low-cost VCXO. The Fox design meets or exceeds typical industry standard specifications & will also drive 8 TTL loads in the 30 ~ 54MHz range. APPLICATIONS FEATURES • Phase-Locked Loops PLLs

H1P transistor with three end

Abstract: SSO20 U2782B U2782B-AFS U2782B-AFSG3 rfd210 SR 13007
Contextual Info: U2782B 1100-MHz Twin PLL Description The IC U2782B is a low-power twin PLL manufactured with Atmel Wireless & Microcontrollers’ advanced UHF process. The maximum operating frequency is 1100 MHz for both PLLs. The device features a wide supply-voltage range from 2.7 V to 5.5 V. A prescaler 64/65 and powerdown function for both PLLs are integrated. The twin

diode F4

Abstract: AN1277 MC145220
Contextual Info: MOTOROLA Order this document by AN1277/D SEMICONDUCTOR TECHNICAL DATA AN1277 Offset Reference PLLs for Fine Resolution or Fast Hopping Prepared by: Morris Smith INTRODUCTION Frequency synthesis by use of two loops, with reference frequencies offset from each other, can provide much finer

U2782B

Abstract: U2782B-AFS U2782B-AFSG3
Contextual Info: Tem ic U2782B S e m i c o n d u c t o r s 1100 MHz Twin PLL Description The IC U2782B is a low power twin PLL manufactured with TEMIC’s advanced UHF process. The maximum operating frequency is 1100 MHz for both PLLs. It features a wide supply voltage range from 2.7 to 5.5 V.

Contextual Info: CDC9171 DVD SYSTEM CLOCK SYNTHESIZER SCAS558B – DECEMBER 1995 – REVISED OCTOBER 1996 D D D D D D D D DB PACKAGE TOP VIEW Two Integrated PLLs Provide All Digital Video Disk (DVD) System Frequencies Two 27-MHz Reference Clock Outputs One 18.432-MHz Reference Clock Output

soc 1044

Contextual Info: DEVICE SPECIFICATION > 4M C SO N E T/SD H /A TM O C -3/12 TR AN SCEIVER W /CDR FEATURES • Complies with ANSI, Bellcore, and ITU-T specifications • On-chip high-frequency PLLs for clock generation and clock recovery • Supports 155.52 MHz OC-3 and 622.08

S3030

Abstract: e4 fault
Contextual Info: JU * EC TARGET SPECIFICATION E4/STM-1/O C-3 ATM T R AN SC EIVER WITH TTL REFCLK FEATURES • • • • • • • • • • • • • GENERAL DESCRIPTION Complies with ANSI, Bellcore, and ITU-T specifications On-chip high-frequency PLLs for clock generation and clock recovery

ICD2062A

Abstract: ICD2062B bt ramdac ICD2062-BSC-2
Contextual Info: fax id: 3502 ICD2062B Dual Programmable ECL/TTL Clock Generator Features • Second generation dual oscillator graphics clock gen­ erator • PECL Video Outputs: 508 kHz to 165 MHz • TTL Outputs: 508 kHz to 120 MHz • Individually programmable PLLs using a highly reli­

laptop motherboard circuit diagram

Abstract: laptop ic list ALL LAPTOP MOTHERBOARD CIRCUIT DIAGRAM ic laptop motherboard ICD2023 spll CY2291 ICD2028 laptop intel MOTHERBOARD CIRCUIT diagram
Contextual Info: Features • Pin compatible with ICD2028 20-pin, 300-mil SOIC . Upward compatible with 2023 (without serial channel), and all versions of 2028 • Three PLLs provide all necessary clocks for modern motherboards and other synchronous systems • Eight outputs including 32 kHz,

LMK04828BISQE

Abstract: LMK04828B
Contextual Info: LMK04826B, LMK04828B www.ti.com SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs Check for Samples: LMK04826B, LMK04828B 1 INTRODUCTION 1.1 Features 12 • JEDEC JESD204B Support

MC145162

Abstract: MC145168 MC145168DW MC145168P MC145169 MC145169DW MC145169P motorola
Contextual Info: MOTOROLA Order this document by MC145168/D SEMICONDUCTOR TECHNICAL DATA MC145168 MC145169 Advance Information Dual PLLs for 46/49 MHz Cordless Telephones CMOS These devices are dual phase–locked loop frequency synthesizers intended for use primarily in 46/49 MHz cordless phones with up to 15 channels. These

DOT96

Abstract: 48MHZ IDTCV110L
Contextual Info: IDTCV110L PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR IDTCV110L DESCRIPTION: FEATURES: IDTCV110L is a 56 pin clock device. The CPU output buffer is designed to support up to 400MHz processor. This chip has three PLLs inside for CPU/

DSA71604

Abstract: LMH1983 720p25 27mhz r
Contextual Info: LMH1983 3G/HD/SD Video Clock Generator with Audio Clock General Description Features The LMH1983 is a highly-integrated programmable audio/ video A/V clock generator intended for broadcast and professional applications. It can replace multiple PLLs and VCXOs used in applications supporting SMPTE serial digital video

phase detector in RTL

Abstract: ADPLL phase detector CH-2555 ADPLL with low jitter
Contextual Info: iniADPLL All Digital Phase Locked Loop Features • • • • • • • • • General Description The iniADPLL is an all digital implementation of a phase locked loop. PLLs are widely used in telecom applications for clock recovery, clock generation and clock supervision. The all digital solution needs no external

LMK04000BISQ

Abstract: LMK04001BISQ LMK04002BISQ LMK04010BISQ LMK04011BISQ LMK04031BISQ LMK04033BISQ
Contextual Info: LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs 1.0 General Description 2.0 Features The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and distribution without the need for high-performance voltage controlled crystal oscillators VCXO module. Using a cascaded

1N4148

Abstract: 2N2222A BLM21A102 GR-253-CORE SY87700V SY87701V dpdt slide switch
Contextual Info: 5V/3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY FEATURES SY87700V DESCRIPTION • 3.3V and 5V power supply options ■ SONET/SDH/ATM compatible ■ Clock and data recovery from 32Mbps up to 175Mbps NRZ data stream ■ Two on-chip PLLs: one for clock generation and

12MHZ

Abstract: SY89420V frequency multiplier SY89420 SY89421V SY89426 EP111
Contextual Info: Single-Chip Programmable Clock PLLs Create 155MHz and 622MHz Frequencies and More! 12MHz – 1.12GHz Wideband PLL ange R t u Inp 0MHz e c eren z – 65 f e R H 12M PLL HFOUT SY89421V Multiplier Select Output Range 12MHz – 1.12GHz FOUT Post Divide FOUT Frequency Select

Contextual Info: MV Series OBSOLETE 14 DIP, 5.0 Volt, HCMOS/TTL, VCXO This product is not recommended for new designs • • • General purpose VCXO for Phase Lock Loops PLLs , Clock Recovery, Reference Signal Tracking, and Synthesizers Frequencies up to 160 MHz

discrete phase sequence detector

Abstract: diode F4 AN1277 MC145220 phase sequence detector
Contextual Info: MOTOROLA Order this document by AN1277/D SEMICONDUCTOR TECHNICAL DATA AN1277 Offset Reference PLLs for Fine Resolution or Fast Hopping Prepared by: Morris Smith INTRODUCTION Frequency synthesis by use of two loops, with reference frequencies offset from each other, can provide much finer

pid-20

Abstract: pid20 PID26 PID23 Pid25 pid11
Contextual Info: Features • Compatible with the ARM7 Family of Processors • Can Directly Connect to the Atmel Implementation of the AMBA™ Peripheral Bus APB • Controls Power Consumption Elements • • • • • • – Main Oscillator – Two Phase Locked Loops (PLLs)

Contextual Info: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig Megafunctions AN-661-3.0 Application Note This application note describes the flow for implementing fractional phase-locked loop PLL reconfiguration and dynamic phase shifting for fractional PLLs in 28-nm

Contextual Info: Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED www.analog.com www.hittite.com THIS PAGE INTENTIONALLY LEFT BLANK New Article Feature by Hittite Microwave Corporation High Performance SiGe PLLs Pair with Low

S1221 AMCC

Abstract: Amcc S1221 ocp sfp SCP6802 SCP6802-GL TRPN03 HFBR-5908E S1201 S1202 S1204
Contextual Info: PRODUC T BRIEF S122 1 S1221 OC-3/12 SONET/SDH 8-bit Quad Transceiver Features Description • CMOS 0.13 micron technology • Complies with Bellcore and ITU-T specifications for jitter tolerance, jitter transfer, and jitter generation • On-chip high-frequency PLLs for clock generation and clock recovery

S19250

Abstract: S19250PB STS-192 S19202CBI20 S19203 S19204 S19227 amcc S19203 rubicon
Contextual Info: PRODUC T BRIEF 50 92 S1 S19250 STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with EDC Features Description • Operational from 9.9 Gbps to 11.3 Gbps • Built-In Self Test BIST with Error Counter • On-chip High-Frequency PLLs for Clock Recovery and Clock Gen.