PID07 Search Results

ma10c

Contextual Info: Oec î j n MOSEL MS400 486SX / 486DX Single Chip AT SEPTEMBER 1991 PRELIMINARY FEATURES DESCRIPTION • Direct Interface to 486SX/487SX or 486DX at speeds from 20-33MHz The MS400 is a highly integrated single chip AT optimized specifically for 486 CPUs. Emphasis has

Contextual Info: 5^E basassi D gdoitgö tt? •■uovi MOSEL MS443 Jntelligent Dual Port Burst Memory PRELIMINARY MOSEL-VITELIC DESCRIPTION FEATURES High Performance Intelligent Memory optimized for fast burst read and burst write operations Compatible with the MOSEL MS441 Concurrent Write

MS6265-10PC

Abstract: MS6265-10NC IT920
Contextual Info: MOSEL MS6265 8K x 8 Slow Speed CMOS Static RAM Ultra Low Data Retention Current FEATURES DESCRIPTION • Available in 100 ns Max. The MOSEL MS6265 is a slow speed, very low data retention current, 64K bit static RAM, organized as 8192 x 8. The MS6265LL is designed to operate over industrial

Contextual Info: FEATURES DESCRIPTION • Fast Access Times: *20/25/35 ns The MS621002 is a high speed 1M-bit static RAM organ ized as 256K x 4. Fully static in operation, the Chip Enable E reduces power to the chip when HIGH. Standby power drops to its lowest level (lSB1) when E is

Contextual Info: MOSEL / — MS62253A 64K x 4 CMOS Static RAM ^ FEATURES DESCRIPTION • Fast Access Times: 20/25 ns The MS62253A is a very high speed 256K-bit static RAM organized as 64K x 4. Fully static in operation. Chip Enable E reduces power to the chip when inactive

Contextual Info: MOSEL MS621002 PRELIMINARY 256K x 4 CMOS Static RAM DESCRIPTION FEATURES The MS621002 is a high speed 1M-bit static RAM organizedas 256K x 4. Fully static in operation, the Chip Enable E reduces power to the chip when HIGH. Standby power drops to its lowest level (lSB1) when E is

Contextual Info: MOSEL MS62251A PRELIMINARY 256K x 1 CMOS Static RAM DESCRIPTION FEATURES The MS62251A is a high speed 262,144 bit static RAM organized as 256K x 1. Fully static in operation, the Chip Enable E reduces power to the chip when HIGH. Standby power drops to its lowest level (lSB1) when E is

Contextual Info: MOSEL MS400 486SX / 486DX Single Chip AT PRELIMINARY FEATURES DESCRIPTION • Direct Interface to 486SX/487SX or 486DX at speeds from 20-33MHZ The MS400 is a highly integrated single chip AT opti­ mized specifically for 486 CPUs. Emphasis has been placed on the cost reduction requirements of 486SX

2943666671

Abstract: fr014 l289 FR2 material data sheet BEAD, WOUND FERRITE, 2943666671 FRQ24 FRQ05 fr024 Video cvbs 656 act ddr2 he ntc
Contextual Info: ADVANCE INFORMA TION KS0123 Data Sheet MULTIMEDIA VIDEO DIGITAL VIDEO ENCODER The KS0123 multi-standard video encoder converts CCIR 656 8-bit multiplexed digital component video into analog baseband signals. It outputs composite video CVBS and S-Video simultaneously at three analog output pins.

Contextual Info: MS61342 FEBRUARY 1992 4K x 8 CMOS Dual Port SRAM FEATURES DESCRIPTION • The MOSEL MS61342 is a 32,768 bit dual port static random access memory organized as 4,096 words by 8 bits allowing each port to independently access any location in memory. A busy flag provides arbitration

Contextual Info: MOSEL MS62253A PRELIMINARY 64K x 4 CMOS Static RAM FEATURES DESCRIPTION Fast Access Times: 20/25 ns The MS62253A is a very high speed 256K-bit static RAM organized as 64K x 4. Fully static in operation. Chip Enable E reduces power to the chip when inactive

Contextual Info: MOSEL MS6265 8K x 8 Slow Speed CMOS Static RAM Ultra Low Data Retention Current FEATURES DESCRIPTION • Available in 100 ns M ax. Th e M O S E L M S 6 2 6 5 is a slow speed, very low data retention current, 6 4 K bit static R A M , organized as 8 1 9 2 x

Contextual Info: MOSEL MS62252A 64K x 4 CMOS Static RAM PRELIMINARY FEATURES DESCRIPTION • The MS62252A is a high speed 262,144 bit static RAM organized as 64K x 4. Fully static in operation, the Chip Enable E reduces power to the chip when HIGH. Standby power (lSB1) drops to its lowest level when E is

Contextual Info: 5ME T> • t.3S33^1 0 D D 1 3 5 3 217 ■ M O V I MOSEL _ M S 6 2 1 0 0 2 PRELIMINARY 256K x 4 CMOS Static RAM MOSEL-VITELIC FEATURES DESCRIPTION • Fast Access Tim es: *20/25/35 ns • Space Saving 400-M il DIP • High Density 400-M il SOJ •

486 system bus

Abstract: cache controller bus architecture 80386 weitek 4167 80386 cache architecture of 80486 MS441 MS443 386 chip set bus ARCHITECTURE OF 80386 data bus, control bus
Contextual Info: MOSEL MS441 Cache Controller PRELIMINARY SimulCache chipset FEATURES DESCRIPTION • High Performance Cache Controller optimized for 486 Secondary cache or 386 Primary cache applications • Integrates two 386/486 bus controllers in combination with Dual Port Burst Memories for Concurrent Write

K321

Abstract: MS621008-20EC MS621008-20KC MS621008-25EC MS621008-35EC
Contextual Info: MOSEL MS621008 P R E L IM IN A R Y 128K x 8 CMOS Static RAM FEATURES DESCRIPTION F a st A c c e s s T im e s : *2 0 /2 5 /3 5 ns T h e M S 6 2 1 0 0 8 is a high s p e e d 1 M -b it s ta tic R AM o rg a n iz e d a s 12 8 K x 8. F u lly s ta tic in o p e ra tio n , th e C hip

MS62252A-25NC

Abstract: MS62252A-25RC MS62252A-35NC MS62252A-35RC MS62252A-45NC PID076
Contextual Info: MOSEL MS62252A PRELIMINARY 64K x 4 CMOS Static RAM FEATURES DESCRIPTION • The M S62252A is a high speed 262,144 bit static RAM o rg a n iz e d ^ 64K x 4. Fully static in operation, the Chip Enable E reduces power to the chip when HIGH. Standby power (lSB1) drops to its lowest level when E is

Contextual Info: MOSEL S62251A PRELIMINARY 256K FEATURES The MS62251A is a high speed 262,144 bit static RAM organized as 256K x 1. Fully static in operation, the Chip Enable E reduces power to the chip when HIGH. Standby power drops to its lowest level (lSBI) when E is

Contextual Info: MOSEL MS621008 PRELIMINARY 128K x 8 CMOS Static RAM DESCRIPTION FEATURES The M S621008 is a high speed 1M-bit static RAM o rganizedas 120K x 8. Fully static in operation, the Chip Enable E control places the RAM in a low-pow er standby mode when inactive (HIGH). Standby power

MS6265

Abstract: H711
Contextual Info: MOSEL /M S6265 8K x 8 Slow Speed CMOS Static RAM Ultra Low Data Retention Current FEATURES DESCRIPTION • Available in 100 ns M ax. • Autom atic power-down when chip disabled Th e M O S E L M S 6 2 6 5 is a slow speed, very low data retention current, 6 4 K bit static R A M , organized as 8 1 9 2 x

weitek

Abstract: weitek 4167 chipset for 486 486 system bus 80386 memory
Contextual Info: baSBBTl DDG17Db DS4 S4E » MOSEL IMO VI MS441 Cache Controller PRELIMINARY SimulCache chipset MO S E L - VITELIC FEATURES DESCRIPTION • High Performance Cache Controller optimized for 486 Secondary cache or 386 Primary cache applications • Integrates two 386/486 bus controllers in combination

Contextual Info: MOSEL p r e lim in a r y MS443 Intelligent Dual Port Burst Memory FEATURES DESCRIPTION • High Performance Intelligent Memory optimized for fast burst read and burst write operations The MOSEL MS443 is an Intelligent Data Path and Cache Memory device optimized for use with MOSEL's

MS441

Abstract: MS443
Contextual Info: M OSEL p r e lim in a r y MS443 Intelligent Dual Port Burst Memory FEATURES DESCRIPTION • High Performance Intelligent M emory optimized for fast burst read and burst write operations The M OSEL M S443 is an Intelligent Data Path and Cache M em ory device optimized for use with MOSEL's

Contextual Info: MOSEL MS621008 PRELIM INARY 128K x 8 CMOS Static RAM DESCRIPTION FEATURES The M S621008 is a high speed 1M -bit static RAM organizedas 128K x 8. Fully static in operation, the Chip Enable E control places the RAM in a low-power standby mode when inactive (HIGH). Standby power