PHY REGISTERS MAP Search Results

Contextual Info: RS825x ATM Physical Interface PHY Devices The RS825x is a family of four 155 Mbps (OC-3/STM-1) ATM-SONET Physical Layer (PHY) devices with an integrated, low-jitter PLL clock and data recovery circuit. These devices have optimized SONET framer functions for mapping ATM cells to SONET

Cx2829

Abstract: A1020 transistor Cx28297 A1020 0x19-RXG1 a1633 J119 J512 j512 data sheet "network interface cards"
Contextual Info: CX28250 ATM Physical Interface PHY Devices The CX28250 is an ATM-SONET Physical Layer (PHY) device with an integrated, PLL clock and data recovery (CDR) circuit. This device has optimized SONET framer functions for mapping ATM cells to SONET payloads for edge switch applications, and

B56A

Abstract: Cx2829 J311 B21AD
Contextual Info: CX28250 ATM Physical Interface PHY Devices The CX28250 is an ATM-SONET Physical Layer (PHY) device with an integrated, PLL clock and data recovery (CDR) circuit. This device has optimized SONET framer functions for mapping ATM cells to SONET payloads for edge switch applications, and

Cx2829

Abstract: TXC24 0x46-RXLIN "network interface cards" Trec Part Numbering System GR
Contextual Info: CX28250 ATM Physical Interface PHY Devices The CX28250 is an ATM-SONET Physical Layer (PHY) device with an integrated, PLL clock and data recovery (CDR) circuit. This device has optimized SONET framer functions for mapping ATM cells to SONET payloads for edge switch applications, and

CX2829

Abstract: J119 J512 A1020 transistor a1633 d705 led CX28250-23 CX28250-26 GR-253-CORE 24V to 15V REGULATOR IC
Contextual Info: CX28250 ATM Physical Interface PHY Devices The CX28250 is an ATM-SONET Physical Layer (PHY) device with an integrated, PLL clock and data recovery (CDR) circuit. This device has optimized SONET framer functions for mapping ATM cells to SONET payloads for edge switch applications, and

Cx2829

Abstract: ,national semiconductor Linear brief lb-3
Contextual Info: CX28250 ATM Physical Interface PHY Devices The CX28250 is an ATM-SONET Physical Layer (PHY) device with an integrated, PLL clock and data recovery (CDR) circuit. This device has optimized SONET framer functions for mapping ATM cells to SONET payloads for edge switch applications, and

8086 hex code

Abstract: PILA8465B 82557 82557 specification update intel 8102 intel application note AP-382 CACHE MEMORY FOR 8086 Intel 82503 82558b
Contextual Info: APPLICATION NOTE AP-382 82557 C-Step and 82558-Based Products EEPROM Address Map and Programming Information Version 1.0 Technical Marketing Network Products Division Intel Corporation May 1997 Copyright 1997 Intel Corporation. All rights reserved. Intel assumes no responsibility for errors or omissions in

IDT88P8344

Abstract: 88P8344
Contextual Info: SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 FEATURES • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation - Maskable interrupts for fatal errors

88E1111 PHY registers map

Abstract: Marvell PHY 88E1111 Datasheet Marvell PHY 88E1111 application note Marvell PHY 88E1111 MDIO read write 88E1111 register map Marvell PHY 88E1111 Xilinx Marvell PHY register map 88E1111 register 88E1111 Marvell 88e1111 register map
Contextual Info: Application Note: Ethernet PHY Register Access With GPIO R XAPP1042 v1.0.1 May 2, 2008 Reference System: Ethernet PHY Register Access With GPIO Author: Brian Hill Abstract The XPS Ethernetlite peripheral does not provide any mechanism to access the Ethernet PHY

TSOP 48 thermal resistance type1

Abstract: IDT88P8342 drw22
Contextual Info: SPI EXCHANGE 2 x SPI-3 TO SPI-4 Issue 1.0 FEATURES • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation - Maskable interrupts for fatal errors

LAN83C694

Abstract: PHY registers map MDIO introduction to auto-negotiation MDO00
Contextual Info: AN 7.9 MII Management Software Implementation for MII Compliant PHYs 1 Introduction This Application Note provides the software developer with the necessary understanding to write software that configures MII compliant PHYs attached to SMSC's FEAST LAN91C100XX or EPIC

ap 8022 b

Abstract: intel 8008 cpu Ap-257 77V011 77V012 77V400 77V500 77V550 AN-257 V400
Contextual Info: Using The 77V011 and SwitchStarTM in a Small Access Switch 77V011 Application Note AN-257 Obective This application note covers the software and hardware configuration for an Access Switch using the 77V011 DPI to U2 translation device and the IDT Switchstar switch fabric. Example register values for programming

pt-041

Abstract: DC028
Contextual Info: DS33Z11 Ethernet Mapper www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS33Z11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 LAPS for transmission over a PDH/TDM data stream. The serial link supports bidirectionalsynchronous interconnect up to 52Mbps over xDSL,

BSP19

Abstract: pt07 SHDSL DS21Q48 DS21Q55 DS3154 DS33Z11 DS33ZH11 RFC1662 BC605
Contextual Info: DS33Z11 Ethernet Mapper www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS33Z11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 LAPS for transmission over a PDH/TDM data stream. The serial link supports bidirectionalsynchronous interconnect up to 52Mbps over xDSL,

7e 33

Contextual Info: DS33Z11 Ethernet Mapper www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS33Z11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 LAPS for transmission over a PDH/TDM data stream. The serial link supports bidirectionalsynchronous interconnect up to 52Mbps over xDSL,

Contextual Info: DS33Z11 Ethernet Mapper www.maxim-ic.com FEATURES GENERAL DESCRIPTION The DS33Z11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 LAPS for transmission over a PDH/TDM data stream. The serial link supports bidirectionalsynchronous interconnect up to 52Mbps over xDSL,

GN4124

Abstract: GN412x PCIe phy C4 to BGA E15 52624 GN4121 GN4124-CBE3
Contextual Info: GN4124 x4 Lane PCI Express to Local Bridge Data Sheet GN4124 x4 Lane PCI Express to Local Bridge Data Sheet 48407 - 1 May 2009 www.gennum.com 1 of 31 Proprietary & Confidential Revision History Version ECR Date Changes and Modifications 2 151915 May 2009 Created new document describing functionality and the register map for GN4124 &

JTAG MODULE SPI

Abstract: spi flash parallel port TSOP 28 SPI memory Package flash 88P8341
Contextual Info: SPI EXCHANGE SPI-3 TO SPI-4 Issue 1.0 FEATURES • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation - Maskable interrupts for fatal errors

ds21348

Abstract: DS33Z rspc DS33Z11 DS33ZH11 RFC1662 169ball
Contextual Info: DS33Z11 Ethernet Mapper www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS33Z11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 LAPS for transmission over a PDH/TDM data stream. The serial link supports bidirectionalsynchronous interconnect up to 52Mbps over xDSL,

MICRO CONTROLLER ATMEL free

Contextual Info: DS33Z11 Ethernet Mapper www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS33Z11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 LAPS for transmission over a PDH/TDM data stream. The serial link supports bidirectionalsynchronous interconnect up to 52Mbps over xDSL,

RFC1662-PPP

Abstract: PADR22 DS33Z11 DS33ZH11 RFC1662 TBC22 BEC20 RPC13 RFC2615-PPP PT041
Contextual Info: DS33Z11 Ethernet Mapper www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS33Z11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 LAPS for transmission over a PDH/TDM data stream. The serial link supports bidirectionalsynchronous interconnect up to 52Mbps over xDSL,

chn 24c02 6

Abstract: TNETE100A TNETE110A SPWU013 chn 24c02 24C02 TNETE211 XL24C02
Contextual Info: ThunderLAN TNETE100A, TNETE110A, TNETE211 Programmer’s Guide October 1996 Network Business Products Printed in U.S.A., October 1996 L411001–9761 revision A SPWU013A t ThunderLAN Programmer’s Guide TNETE100A, TNETE110A, TNETE211 Literature Number: SPWU013A

DS21455

Abstract: DS21458 DS26528 DS33Z11 DS33Z41 RFC1662 G.SHDSL Industry Single-Chip 0301H 4BC20
Contextual Info: DS33Z41 Quad IMUX Ethernet Mapper www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS33Z41 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 LAPS for transmission over up to four interleaved PDH/TDM data streams using robust,

lxt971a

Abstract: 302875 "network interface cards"
Contextual Info: Cortina Systems LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet The Cortina Systems® LXT972M Single-Port 10/100 Mbps PHY Transceiver LXT972M PHY directly supports both 100BASE-TX and 10BASE-T applications. The LXT972M PHY is IEEE compliant and