PHASELINK PLL202 Search Results

METABO

Contextual Info: Reducing EMI with PhaseLink’s Spread Spectrum Technology Revised Sep. 2001 EMI - Electro-Magnetic Interference • Electromagnetic waves generated by electric signals – Particularly: frequency generators, clock chips. – Depending on source: • different frequency spectrum

PLL202-11

Contextual Info: AN-202-11B-11C PLL 202-11B and PLL202-11C Comparison PRODUCT STATUS The PLL202-11C is a fully compatible replacement part to the PLL202-11B. All characteristics are kept identical except for the frequency switching characteristics and internal pullup resistor values on pins 23 and 24. Both changes are detailed hereafter.

24mhz crystal 14pin dip

Abstract: PLL202-02 phaselink pll202 LL2020 by 02 be 48MHZ
Contextual Info: Preliminary PLL202-02 System Clock Generator for various SOC FEATURES • Generates all clock frequencies for multiple CPU clocks and various SOC. Support one CPU clock. One 24MHz clock and one 48MHz clock. One 14.318MHz reference clocks. 3.3V operation; 50% percent duty cycle.

440BX

Abstract: PLL202-01
Contextual Info: PLL202-01 Motherboard Clock Generator for 440BX Type with 133MHz FSB FEATURES • • • • • • • Generates all clock frequencies for PentiumΙΙΙ systems with INTEL 440BX or VIA Apollo Pro133 or Promedia chip sets, requiring multiple CPU clocks and high speed SDRAM buffers.

PLL103-02

Abstract: PLL202-04
Contextual Info: PLL202-04 Programmable Clock Generator for VIA Apollo Pro-266 FEATURES • • • • • • Generates all clock frequencies for PentiumΙΙ/ΙΙΙ system processor. Support 3 CPU clocks, 3 AGP and 9 PCI. Enhanced PCI Output Drive selectable by I2C. One 48MHz clock or 24_48MHz clock via I2C .

sis630

Abstract: 48MHZ PLL202-03 SIS540
Contextual Info: PLL202-03 Motherboard Clock Generator for SIS540/630 with 133MHz FSB FEATURES • • • • • • • • • Generates all clock frequencies for SIS540, SIS630 Pentium ΙΙ/ΙΙΙ and K6 chip sets, requiring multiple CPU clocks and high speed SDRAM buffers.

PLL103-07

Abstract: PLL202-04
Contextual Info: Preliminary PLL103-07 2 DIMM DDR Fanout Buffer FEATURES Generates 12-output buffers from one input. Supports VIA Pro266 DDR chipset. Supports up to 2 DDR DIMMS. Supports up to 400MHz DDR, SDRAMS. One additional output for feedback. 6 differential clock distribution.

ddr5

Abstract: PLL103-02 PLL202-04 ddr-7-t
Contextual Info: PLL103-02 Rev.D DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS FEATURES Generates 24 output buffer from one input. Supports up to four DDR DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback. Less than 5ns delay. Skew between any outputs is less than 100 ps.

EMI-01

Abstract: PLL701-04 PLL701-14
Contextual Info: Application Note EMI-01 USING SPREAD SPECTRUM TECHNOLOGY TO REDUCE EMI AND LOWER COSTS INTRODUCTION Electromagnetic Interferences EMI are subject to very strict regulations by US (FCC) and other international regulatory bodies (EN, etc.). These regulations aim at limiting the amount of EMI electronic devices emit, and at preventing interference between electronic devices, and

SIS630

Abstract: SiS540 48MHZ PLL202-13
Contextual Info: PLL202-13 Motherboard Clock Generator for SIS540/630 with 133MHz FSB FEATURES • • • • • • • • • • Generates all clock frequencies for SIS540, SIS630 Pentium ΙΙ and K6 chip sets, requiring multiple CPU clocks and high speed SDRAM buffers.

PLL103-06

Abstract: PLL202-04
Contextual Info: Preliminary PLL103-06 DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS FEATURES • • • Generates 12-output buffers from one input. Supports up to 2 DDR DIMMS or 3 SDRAM DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback. Less than 5ns delay.

ddr5

Abstract: PLL103-02 PLL202-04
Contextual Info: PLL103-02 DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS FEATURES • • • Generates 24 output buffer from one input. Supports up to four DDR DIMMS or 2 SDRAM DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback. Less than 5ns delay.

PLL202-11

Contextual Info: PLL202-11 rev. D Motherboard Clock Generator for 440BX Type with 133MHz FSB FEATURES • • • • • • • Generates all clock frequencies for PentiumΙΙΙ systems with INTEL 440BX or VIA Apollo Pro133 or Promedia chip sets, requiring multiple CPU clocks and high speed SDRAM buffers.

PLL202-11

Abstract: phaselink pll202-11
Contextual Info: PLL202-11 Motherboard Clock Generator for 440BX Type with 133MHz FSB FEATURES • • • • • • • Generates all clock frequencies for PentiumΙΙΙ systems with INTEL 440BX or VIA Apollo Pro133 or Promedia chip sets, requiring multiple CPU clocks and high speed SDRAM buffers.

PLL103-53

Abstract: DDR6
Contextual Info: Preliminary PLL103-53 DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS FEATURES • • • Generates 30-output buffers from one input. Supports up to 4 DDR DIMMS or 3 SDR DIMMS and 2 DDR DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback.

PLL103-03

Abstract: PLL202-04
Contextual Info: Preliminary PLL103-03 DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS FEATURES • • • Generates 24-output buffers from one input. Supports up to 4 DDR DIMMS or 3 SDR DIMMS and 2 DDR DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback.

PLL202-54

Abstract: PLL2025
Contextual Info: PLL202-54 Programmable Clock Generator for VIA Apollo Pro-266 with VID FEATURES • • • • • • • • Generates all clock frequencies for PentiumΙΙ/ΙΙΙ system processor. Support 3 CPU clocks, 3 AGP and 9 PCI. Enhanced PCI Output Drive selectable by I2C.

PLL103-02

Abstract: PLL202-14
Contextual Info: PLL202-14 Programmable Clock Generator for VIA Apollo Pro-266 FEATURES • • • • • • • Generates all clock frequencies for PentiumΙΙ/ΙΙΙ system processor. Support 3 CPU clocks, 3 AGP and 9 PCI. Enhanced PCI Output Drive selectable by I2C.

6 bit divider

Abstract: ALI chipset PLL202-108 SEL24
Contextual Info: PLL202-108 Programmable Clock Generator for ALI 1681 P4 Chip Sets PIN CONFIGURATION FEATURES • • • • • • • • • • • BLOCK DIAGRAM XIN XOUT VDDCPU CPUT 0:1 CPUC (0:1) CPUSTP# PCISTP# MULTSEL HTTSEL FS(0:3) PLL1 SST Control Logic Note:

SIS 650

Abstract: sis 648 48MHZ PLL202-107 ZCLK0
Contextual Info: PLL202-107 Programmable Clock Generator for SIS 645/650 P4 Chip Sets PIN CONFIGURATION FEATURES • • • • • • • • • • • BLOCK DIAGRAM XIN XOUT VDD_CPU CPU_STOP# CPUT 0:1 CPUC (0:1) PCI_STOP# MULTSEL PD# FS(0:4) VDD PLL1 SST Control Logic

Contextual Info:

      

 • • • • • • Clock frequency generator for VIA Pentium4 chipsets. Provides 1 REF clock, 3 CPU including one at 2.5V for the Chipset , 3 AGP, and 9 PCI clocks. One 48MHz clock, one 24_48MHz clock.

ALI chipset

Abstract: KM266 SIS 650 Via KM266 48MHZ M1671 PLL202-151 ali m1671 KM26
Contextual Info: PRELIMINARY PLL202-151 Programmable Clock Generator for VIA, ALI and SIS DDR SYSTEM FEATURES • • • • • • • • • • • • • Supports VIA P4M/KM266, ALI M1671 and SIS 645/650 Chipsets. Programmable Spread Spectrum Modulation from ±0.1% to ±1.5% with minim u m step size of

m16811

Abstract: u48 PMU ICS952501 BT135 1001 dl pwm quanta T210P 12Bst MAX8863SEUK T quanta computer
Contextual Info: 1 2 3 4 5 6 CPUCLK+ CPUCLK- Power - Source Control HCLK+ HCLK- CPU CORE Power PAGE 41. PAGE 38. PCLK_MPCI ICS952501 (PLL202-108) PCLK_1394 MCLK PCLK_591 A PCLK_SB CLOCKS buffer (ICS93735) (PLL102-108) GCLK PAGE 40. PCI BUS Routing Table =