The Datasheet Archive

PLL202-14 datasheet (4)

Part Manufacturer Description Type PDF
PLL202-14 PhaseLink Ali Via Sis Intel 440BX Chipset FTGS Freq. Progr. Power Mgt Wdt Drive Ctrl SST Original PDF
PLL202-14XC PhaseLink Programmable Clock Generator for VIA Apollo Pro-266 Original PDF
PLL202-14XI PhaseLink Programmable Clock Generator for VIA Apollo Pro-266 Original PDF
PLL202-14XM PhaseLink Programmable Clock Generator for VIA Apollo Pro-266 Original PDF

PLL202-14 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
PLL103-02

Abstract: PLL202-14
Text: PLL202-14 Programmable Clock Generator for VIA Apollo Pro-266 FEATURES · · · · · · · , 26 AGP2 AGP1 VDD3 24 25 GND PLL202-14 · · · · · PIN CONFIGURATION , ) 492-0990 FAX (510) 492-0991 Rev 3/23/01 Page 1 PLL202-14 Programmable Clock Generator for VIA , , California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 3/23/01 Page 2 PLL202-14 Programmable , FAX (510) 492-0991 Rev 3/23/01 Page 3 PLL202-14 Programmable Clock Generator for VIA Apollo


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PDF PLL202-14 Pro-266 48MHz 318MHz PLL103-02 PLL202-14
6 bit divider

Abstract: ALI chipset PLL202-108 SEL24
Text: ), 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 v: 48 , will be generated after watchdog timer expires if I2C Enable bit (Byte9.bit7) is set active 13, 14 , 14 ,286 -0.5% down 400 0.60 14 ,286 33.33 -0.5% down 400 0.90 14 ,286 , 0.30 14 ,286 90.00 60.00 30.00 30.00 ±0.3% center 360 0.45 12,857 0 , 33.67 ±0.3% center 404 0.45 14 ,429 1 0 0 1 134.67 67.33 33.67 33.67


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PDF PLL202-108 6 bit divider ALI chipset PLL202-108 SEL24
SIS630

Abstract: SiS540 48MHZ PLL202-13
Text: , requiring multiple CPU clocks and high speed SDRAM buffers. Support 3 CPU clocks, 7PCI and 14 high-speed , 44 6 43 7 8 42 41 9 10 11 12 13 14 15 16 17 PLL202-13 · PIN , output clocks. They have internal pull down (low by default). PCI (0:6) 7,8,9,11,12, 13, 14 O , up latched CPU2.5_3.3 value (Read-back only) Bit 6 14 1 PCI6 ( Active/Inactive ) Bit 5 , ., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 ps Rev 02/15/00 Page 14 PLL202


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PDF PLL202-13 SIS540/630 133MHz SIS540, SIS630 48MHz Two14 318MHz SiS540 PLL202-13
PLL103-02

Abstract: PLL202-04
Text: 37 36 VDDL2 GND PCI3 VDD3 14 15 35 34 CPU2 CPU_STOP PCI4 PCI5 16 17 , When input is LOW, CPU_STOP will stop CPU(0:2). PCI_F, PCI(0:7) 9,10,11,13, 14 , 16,17,18,20 O , PCI4 ( Active/Inactive ) Bit 3 14 1 PCI3 ( Active/Inactive ) Bit 2 13 1 PCI2


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PDF PLL202-04 Pro-266 48MHz Two14 318MHz PLL103-02 PLL202-04
PLL202-54

Abstract: PLL2025
Text: 55 54 9 10 11 12 PCI2 PCI3 VDD3 13 14 15 16 17 GND APIC2 49 48 7 8 , , CPU_STOP will stop CPU(0:2). PCI_F, PCI(0:7) 9,10,11,13, 14 , 16,17,18,20 O PCI clocks with , /Inactive ) Bit 3 14 1 PCI3 ( Active/Inactive ) Bit 2 13 1 PCI2 ( Active/Inactive , /00 Page 14 PLL202-54 Programmable Clock Generator for VIA Apollo Pro-266 with VID 2. DC/AC


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PDF PLL202-54 Pro-266 48MHz 318MHz PLL202-54 PLL2025
PLL202-11XC

Abstract: PLL202-11 diagram motherboard
Text: 8 42 41 9 10 11 12 13 14 15 16 40 39 38 37 36 35 34 33 17 18 32 31 , , REF1, and crystal oscillator. VDD2 6, 14 P Power supply for PCI_F, PCI(0:4). VDD3 19 , ) 492-0991 Rev E 12/04/00 Page 14 PhaseLink


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PDF PLL202-11 440BX 133MHz Pro133 24MHz 48MHz Two14 318MHz PLL202-11XC diagram motherboard
PLL202-11

Abstract: phaselink pll202-11
Text: 8 42 41 9 10 11 12 13 14 15 16 40 39 38 37 36 35 34 33 17 18 32 31 , crystal oscillator. VDD2 6, 14 P Power supply for PCI_F, PCI(0:4). VDD3 19,30,36 P , Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/26/00 Page 14


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PDF PLL202-11 440BX 133MHz Pro133 24MHz 48MHz Two14 318MHz PLL202-11 phaselink pll202-11
SIS 650

Abstract: sis 648 48MHZ PLL202-107 ZCLK0
Text: : Pull Up (120k), 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 , . PCIF[0:1]/FS[3:4] 14 ,15 B Bi-directional pin. At power-up, the FS[3:4] input value is latched , N 400 0.30 14 ,303 ±0.3% center 400 0.45 14 ,303 33.35 ±0.3% center 667 0.30 23,851 66.67 33.33 ±0.3% center 400 0.45 14 ,303 133.33 66.67 33.33 ±0.3% center 400 0.45 14 ,303 133.40 133.40 66.70 33.35 ±0.3% center 667


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PDF PLL202-107 VDD48M 48MHz 48MHz/MULTSEL* VSS48M SIS 650 sis 648 48MHZ PLL202-107 ZCLK0
sis630

Abstract: 48MHZ PLL202-03 SIS540
Text: , requiring multiple CPU clocks and high speed SDRAM buffers. Support 3 CPU clocks, 7PCI and 14 high-speed , 10 11 12 13 14 15 16 17 PLL202-03 · PIN CONFIGURATION 40 39 38 37 36 35 34 , :6) 7,8,9,11,12, 13, 14 O PCI clocks with frequencies defined by Frequency Table. CPU (0 , up latched CPU2.5_3.3 value (Read-back only) Bit 6 14 1 PCI6 ( Active/Inactive ) Bit 5


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PDF PLL202-03 SIS540/630 133MHz SIS540, SIS630 48MHz Two14 318MHz PLL202-03 SIS540
PLL202-11

Abstract: No abstract text available
Text: 8 42 41 9 10 11 12 13 14 15 16 40 39 38 37 36 35 34 33 17 18 32 31 , , REF1, and crystal oscillator. VDD2 6, 14 P Power supply for PCI_F, PCI(0:4). VDD3 19 , ) 492-0991 Rev D 10/19/00 Page 14 PhaseLink


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PDF PLL202-11 440BX 133MHz Pro133 24MHz 48MHz Two14 318MHz
24mhz crystal 14pin dip

Abstract: PLL202-02 phaselink pll202 LL2020 by 02 be 48MHZ
Text: in 14 -pin 300mil DIP. GND 14 1 XIN 2 XOUT 3 VDD 4 GND 5 GND 6 , ,9,10, 14 P 3.3V Power supply. CPU 11 O CPU clocks with frequencies defined by , INFORMATION 14 P IN DIP ORDERING INFORMATION For part ordering, please contact our Sales Department


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PDF PLL202-02 24MHz 48MHz 318MHz 14-pin 300mil 24MHz/FS LL202-02 48MHz/FS 24mhz crystal 14pin dip PLL202-02 phaselink pll202 LL2020 by 02 be
440BX

Abstract: PLL202-01
Text: 48 47 3 4 46 45 5 6 44 43 7 8 42 41 9 10 11 12 13 14 15 16 , Power supply for REF0, REF1, and crystal oscillator. VDD2 6, 14 P Power supply for PCI_F, PCI


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PDF PLL202-01 440BX 133MHz Pro133 24MHz 48MHz Two14 318MHz PLL202-01
PLL202-11

Abstract: No abstract text available
Text: No file text available


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PDF AN-202-11B-11C 202-11B PLL202-11C PLL202-11B. PLL202-11B, PLL202-11
ALI chipset

Abstract: KM266 SIS 650 Via KM266 48MHZ M1671 PLL202-151 ali m1671 KM26
Text: ) PLL1 SST Control Logic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 , is selected If SEL_SDR_DDR=1, SDRAM mode is selected. 14 ,15,17,18 O PCI clock output (see , =Inactive) Bit 4 15 1 PCI3 (1=Active 0=Inactive) Bit 3 14 1 PCI2 (1=Active 0 , :0> = Modulation rate * N /7 Down Spread: SST<6:0> = Modulation rate * N / 14 TEL (510) 492-0990 , for VIA, ALI and SIS DDR SYSTEM 14 . SKEW Control Register (1=Enable, 0=Disable) Byte # Bit


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PDF PLL202-151 P4M/KM266, M1671 ALI chipset KM266 SIS 650 Via KM266 48MHZ PLL202-151 ali m1671 KM26
PLL103-53

Abstract: DDR6
Text: and 2 DDR DIMMS. The PLL103-53 can be used in conjunction with the PLL202-14 /-54 or similar clock , 14 15 DDR3C_SDRAM5 VDD3.3_2.5 16 17 GND DDR4T_SDRAM6 18 19 39 38 GND DDR7T , =0. STANDARD SDRAM mode is selected. VDD2.5 32,40,45, 49,55 P 2.5V power supply. GND 3,9, 14


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PDF PLL103-53 30-output 266MHz SDRAM10 SDRAM11 DDR11T DDR11C DDR10T DDR10C PLL103-53 DDR6
Not Available

Abstract: No abstract text available
Text: x IREF, 1 selects Ioh = 6 x IREF. This pin has a 100k internal pull-up. PCI(2:7) 14 ,15,17 , ) Bit 3 15 1 PCI3 ( Active/Inactive ) Bit 2 14 1 PCI2 ( Active/Inactive ) Bit 1 , /01 Page 14 # 0' " ! ; < Unless otherwise stated, all power supplies =


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PDF 48MHz 318MHz
ddr5

Abstract: PLL103-02 PLL202-04
Text: SDATA SCLK I2C Control 12 13 GND DDR3T_SDRAM4 14 15 DDR3C_SDRAM5 VDD3.3_2.5 16 , selected. VDD2.5 32,37,41,47 P 2.5V power supply. GND 3,9, 14 ,18,26, 31,35,40,46 P


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PDF PLL103-02 266MHz DDR11T DDR11C DDR10T DDR10C ddr5 PLL103-02 PLL202-04
PLL103-03

Abstract: PLL202-04
Text: DDR3T_SDRAM4 13 14 36 35 PD# GND 34 33 DDR8T DDR8C PLL103-03 · · · · · · PIN , P 2.5V power supply. GND 3,9, 14 ,18,26 , 31,35,40,46 P Ground. 47745 Fremont Blvd


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PDF PLL103-03 24-output 266MHz SDRAM10 DDR11T SDRAM11 DDR11C DDR10T DDR10C PLL103-03 PLL202-04
PLL103-06

Abstract: PLL202-04
Text: DDR5C_SDRAM11 FBOUT SEL_DDR GND 13 16 SCLK 14 15 SDATA Note: #: Active Low , swing depends on VDD3.3_2.5. VDD3.3_2.5 5,9, 14 ,21,25 P When VDD=2.5V, SEL_DDR=1. DDR-ONLY


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PDF PLL103-06 12-output 266MHz SDRAM10 SDRAM11 PLL103-06 PLL202-04
PLL103-07

Abstract: PLL202-04
Text: 18 12 13 16 SCLK VDD2.5 DDR0T 11 DDRT2 BLOCK DIAGRAM 14 15 SDATA , pair outputs. VDD2.5 5,9, 14 , 17,21,25 P 2.5V power supply. GND 6,11,20,24 P


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PDF PLL103-07 12-output Pro266 400MHz 28-pin PLL103-07 PLL202-04
ddr5

Abstract: PLL103-02 PLL202-04 ddr-7-t
Text: GND DDR9T DDR2C VDD2.5 11 12 38 37 DDR9C VDD2.5 BUF_IN GND DDR3T 13 14 36 , of BUF_IN. VDD2.5 2,8,12,17,23, 32,37,41,47 P 2.5V power supply. GND 3,9, 14 ,18,26


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PDF PLL103-02 266MHz DDR11T DDR11C DDR10T DDR10C ddr5 PLL202-04 ddr-7-t
15SP 016

Abstract: tb 1229 bn tda 2022 2N1150 P96-P97 PMC8316 dtc114 PCS17 nec d299 W134
Text: 11.309 11.309 11.309 11.310 11.A/D.311 14 U14985JJ2V0UM 12.313 , -10TM40. 242 -11. -12. -13. - 14 . 244 244 245 246 -15. -16PWM. -17PWM. , 100LQFP14×14 U14985JJ2V0UM ROM 33 MHz HVDD 4.55.5 V .Top View 100 LQFP14× 14 75 74 , 49 50 AVDD AVSS AVREF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 , ROM DRAM BCT .BCT 16 15 BCT 14 13 12 11 10 9 8 7 6 5 4


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PDF V850E/MS2TM PD703130 U14985JJ2V0UM00 U14985JJ2V0UM 12A0-A15Address0-15. 13D0-D7Data0-7. 10AVDD 11AVSS 15SP 016 tb 1229 bn tda 2022 2N1150 P96-P97 PMC8316 dtc114 PCS17 nec d299 W134
m16811

Abstract: BT135 u48 PMU ICS952501 1001 dl pwm 12Bst quanta T210P DTSMW-64 DC148
Text: 25. ATA 66/100/133 South - Bridge ALi M1563 PAGE 12,13, 14 . CARDBUS OZ711M2 PAGE 21,22,23 , G25 P26 V21 A#3 A#4 A#5 A#6 A#7 A#8 A#9 A#10 A#11 A#12 A#13 A# 14 A#15 A#16 A#17 A#18 A#19 A#20 A#21 A , #8 D#9 D#10 D#11 D#12 D#13 D# 14 D#15 D#16 D#17 D#18 D#19 D#20 D#21 D#22 D#23 D#24 D#25 D#26 D#27 D#28 D , P23 R22 W23 W22 A20M# FERR# CPUINIT# INTR NMI IGNNE# SMI# SLP# STPCLK# A20M# { 14 } FERR# { 14 } CPUINIT# { 14 } INTR { 14 } NMI { 14 } IGNNE# { 14 } SMI# { 14 } SLP# { 14 } STPCLK# { 14 } ADS# {4} HA_STB0# {4} HA_STB1# {4


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PDF ICS952501) PLL202-108) M1681 M1563 USB20 ICS93735) PLL102-108) ISL6207 1U25V m16811 BT135 u48 PMU ICS952501 1001 dl pwm 12Bst quanta T210P DTSMW-64 DC148
C9847

Abstract: MMD41 C2792 foxconn MMD50 MMD54 29C04 CB1410-B0 MMD56 VT1612
Text: 14 : CB-1410 CONTROLLER PAGE 15 : MINI PCI & PCMCIA CONN. PAGE 16 : 1394a PAGE 17 : LAN PAGE 18 : LPC , VT8235 SOUTH BRIDGE PAGE 8,9,10 X'TAL 32KHz MINI-PCI PAGE 15 PAGE CARDBUS ENE 1410+2211 14 , VTT R564 1 R565 1 AF18 2 1NCHCTRL AD16 R110 14 1%_0402 AE8 N24 AE10 2 1K_0402 AF11 2 1K_0402 E2 P4 , E A 7 of 33 A B C D E 14 ,15,16 AD[0.31] AD[0.31] U38A AD0 AD1 AD2 AD3 , 1 1 1 1 1 1 1 1 OC4# OC5# 14 ,15,16 CBE#[0.3] R378 USBREXT USBCLK


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PDF TPC02 CB-1410 1394a PC87591 MAX1999) 2N7002 2N7002 CPU1V25 10uF/25V C9847 MMD41 C2792 foxconn MMD50 MMD54 29C04 CB1410-B0 MMD56 VT1612
2010 - TMP38

Abstract: IR p613 DL78 d1616 a V850ES PCT398 uPD70F3745 uPD70F3744 uPD70F3743 IR p615
Text: .116 4. 3. 14 DH , .459 13. 1 13. 2 13. 3 13. 4 13. 5 14 14 . 1 14 . 2 14 . 3 14 . 4 D/A , .466 14 . 4. 1 .466 14 . 4. 2 .466 14 . 4. 3 , .548 16. 6. 14


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PDF V850ES/JJ3 PD70F3743 PD70F3744 PD70F3745 PD70F3746 V850ES V850ES/JJ TMP38 IR p613 DL78 d1616 a V850ES PCT398 uPD70F3745 uPD70F3744 uPD70F3743 IR p615
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