PEEL GATE ARRAY LOGIC Search Results

18CV8

Contextual Info: -> GOULD CHIOSE*PLD Electrically ErasableProgrammableLogic PEEL 18CV8 Features • Synchronous preset, asynchronous clear • Independent output enables Advanced CMOS E2PROM Technology Application Versatility • Replace SSI/MSI logic • Emulates bipolar PAL™, GAL™ and the EPLDS

altera EP300

Abstract: 18CV8 18cv8 programming altera ep 18cv8s 10391-D
Contextual Info: GOULD SEMIC ONDU CTOR DIV 03E D | MDSSilti □□103S2 4055916 GOU LD S EM IC O N D U C T OR DIV -> GOULO Electronics 03E 10382 D CMOS e 2p l d Electrically Erasable Programmable Logic PEEL 18CV8 Features • Synchronous preset, asynchronous clear • Independent output enables

18CV8

Abstract: 18CV825 18CV815 18cv8 programming 18CV8-15 HAS64 PEEL18CV8 AMI PEEL18CV8
Contextual Info: AMI PEEL 18CV8 SEMICONDUCTORS February 1993 CMOS Programmable Electrically Erasable Logic Device General Description Features The AMI PEEL18CV8 is a CMOS Programmable Electrically Erasable Logic device that provides a highperformance, low-power, reprogrammable,

22CV10

Abstract: 22CV10A PAL22V10 PEEL22LV10AZJ-25 PEEL22LV10AZP-25 PEEL22LV10AZS-25 PEEL22LV10AZT-25
Contextual Info: PEEL 22LV10AZ -25 CMOS Programmable Electrically Erasable Logic Device Features Low Voltage, Ultra Low Power Operation - Vcc = 2.7 to 3.6 V - Icc = 5 µA typical at standby - Icc = 1.5 mA (typical) at 1 MHz - Meets JEDEC LV Interface Spec (JESD8-A) - 5 Volt tolerant inputs and I/O’s

PEEL18CV8P-15

Abstract: PEEL18CV8S-7
Contextual Info: Not recommended for New designs contact factory for availability PEEL 18CV8 -7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features Architectural Flexibility - Enhanced architecture fits in more logic - 74 product terms x 36 input AND array

PEEL18CV8P-15

Abstract: PEEL18CV8J-10 PEEL18CV8P 18CV8 PEEL18CV8P-25L PEEL18CV PEEL18CV8J-25 PEEL18CV8JI-25 PEEL18CV8P-25 PEEL18CV8J-7
Contextual Info: PEEL 18CV8 -7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features Architectural Flexibility - Enhanced architecture fits in more logic - 74 product terms x 36 input AND array - 10 inputs and 8 I/O pins - 12 possible macrocell configurations

ICT 18CV8Z

Abstract: ICT PEEL18CV8ZP-25 18CV8Z-25 16V8 18CV8 PAL16V8 PEEL18CV8ZJ-25 PEEL18CV8ZP-25 PEEL18CV8ZJI-25
Contextual Info: Commercial PEEL 18CV8Z-25 CMOS Programmable Electrically Erasable Logic Device Features • Ultra Low Power Operation - Vcc = 5 Volts ±10% - Icc = 10 µA typical at standby - Icc = 2 mA (typical) at 1 MHz ■ CMOS Electrically Erasable Technology - Superior factory testing

PAL16V8

Abstract: 16V8 18CV8 PEEL18CV8ZJ-25 PEEL18CV8ZP-25 PEEL18CV8ZS-25 18CV8Z-25
Contextual Info: PEEL 18CV8Z-25 CMOS Programmable Electrically Erasable Logic Device Features • Ultra Low Power Operation - Vcc = 5 Volts ±10% - Icc = 10 µA typical at standby - Icc = 2 mA (typical) at 1 MHz ■ CMOS Electrically Erasable Technology - Superior factory testing

18CV8

Abstract: PEEL18CV8J-7 PEEL18CV8P-7 PEEL18CV8S-7 PEEL18CV8P-10
Contextual Info: PEEL 18CV8 -7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features • Multiple Speed Power, Temperature Options - VCC = 5 Volts ±10% - Speeds ranging from 7ns to 25 ns - Power as low as 37mA at 25MHz - Commercial and industrial versions available

18cv8z-25

Abstract: PEELTM18CV8Z PEEL18CV8ZJI PEEL18CV8ZJI-25
Contextual Info: Commercial PEEL 18CV8Z-25 CMOS Programmable Electrically Erasable Logic Device Features • Ultra Low Power Operation - Vcc = 5 Volts ±10% - Icc = 10 µA typical at standby - Icc = 2 mA (typical) at 1 MHz ■ CMOS Electrically Erasable Technology - Superior factory testing

Contextual Info: Commercial PEEL 22LV10AZ -25 CMOS Programmable Electrically Erasable Logic Device Features • Low Voltage, Ultra Low Power Operation - Vcc = 2.7 to 3.6 V - Icc = 5 µA typical at standby - Icc = 1.5 mA (typical) at 1 MHz - Meets JEDEC LV Interface Spec (JESD8-A)

22CV10

Abstract: 22CV10A PAL22V10 PEEL22LV10AZJ-25 PEEL22LV10AZP-25 biomedical
Contextual Info: PEEL 22LV10AZ -25 CMOS Programmable Electrically Erasable Logic Device Features • Low Voltage, Ultra Low Power Operation - Vcc = 2.7 to 3.6 V - Icc = 5 µA typical at standby - Icc = 1.5 mA (typical) at 1 MHz - Meets JEDEC LV Interface Spec (JESD8-A)

22CV10

Abstract: 22CV10A PAL22V10 PEEL22LV10AZJ-25 PEEL22LV10AZP-25 PEEL22LV10AZS-25
Contextual Info: PEEL 22LV10AZ -25 CMOS Programmable Electrically Erasable Logic Device Features Low Voltage, Ultra Low Power Operation - Vcc = 2.7 to 3.6 V - Icc = 5 µA typical at standby - Icc = 1.5 mA (typical) at 1 MHz - Meets JEDEC LV Interface Spec (JESD8-A) - 5 Volt tolerant inputs and I/O’s

Contextual Info: Commercial PEEL 18LV8Z -25 CMOS Programmable Electrically Erasable Logic Device Features • Low Voltage, Ultra Low Power Operation - Vcc = 2.7 to 3.6 V - Icc =5 µA typical at standby - Icc = 1.5 mA (typical) at 1 MHz - Meets JEDEC LV Interface Spec (JESD8-A)

Contextual Info: To Notfind recommended out if the package for New you designs need isavailable, contactcontact factoryCustomer for availability Service PEEL 22LV10AZ -25 CMOS Programmable Electrically Erasable Logic Device Features Low Voltage, Ultra Low Power Operation

Contextual Info: To find out if the package you need is available, contact Customer Service PEEL 22LV10AZ -25 CMOS Programmable Electrically Erasable Logic Device Features Low Voltage, Ultra Low Power Operation - Vcc = 2.7 to 3.6 V - Icc = 5 µA typical at standby - Icc = 1.5 mA (typical) at 1 MHz

PAL16V8

Abstract: 16V8 18CV8 PEEL18CV8ZJ-25 PEEL18CV8ZP-25 PEEL18CV8ZS-25 PEEL18CV8ZJ25 PEEL18CV8ZP-25L
Contextual Info: PEEL 18CV8Z -25 CMOS Programmable Electrically Erasable Logic Device Features Ultra Low Power Operation - Vcc = 5 Volts ±10% - Icc = 10 µA typical at standby - Icc = 2 mA (typical) at 1 MHz Architectural Flexibility - Enhanced architecture fits in more logic

pal16v8

Abstract: dec mer PEEL18CV8ZP-25L
Contextual Info: ic PEEL 18CV8Z -25 CMOS Programmable Electrically Erasable Logic Device Features Ultra Low Power Operation - Vcc = 5 Volts ±10% - Icc = 10 µA typical at standby - Icc = 2 mA (typical) at 1 MHz Architectural Flexibility - Enhanced architecture fits in more logic

ICT 18CV8

Abstract: 18CV8 PEEL18CV8P-15 ICT 20 PIN PLASTIC 300 MIL DIP programmer EPLD 18cv8 programming free circuit eeprom programmer PEEL18CV PEEL18CV8J-5 PEEL18CV8P-7
Contextual Info: Commercial/ Industrial PEEL 18CV8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features • Multiple Speed Power, Temperature Options - VCC = 5 Volts ±10% - Speeds ranging from 5ns to 25 ns - Power as low as 37mA at 25MHz - Commercial and industrial versions available

Contextual Info: Preliminary Commercial PEEL 22LV10AZ-25 CMOS Programmable Electrically Erasable Logic Device FEATURES • Low Voltage, Ultra Low Power Operation - Vcc = 2.7 to 3.6 V - Icc =25 uA typical at standby - Icc = 2 mA (typical) at 1 MHz - Meets JEDEC LV Interface Spec (JESD8-A)

Contextual Info: Preliminary Commercial PEEL 18LV8Z-25 CMOS Programmable Electrically Erasable Logic Device FEATURES • Low Voltage, Ultra Low Power Operation - Vcc = 2.7 to 3.6 V - Icc =25 uA typical at standby - Icc = 2 mA (typical) at 1 MHz - Meets JEDEC LV Interface Spec (JESD8-A)

ict peel 18cv8

Abstract: PEEL18CV8P-25 ICT 18CV8 ICT Peel programmer EPLD 18CV8 low cost eeprom programmer circuit diagram PEEL18CV PEEL18CV8 PEEL18CV8J-5
Contextual Info: Commercial/ Industrial PEEL18CV8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features • Multiple Speed, Power, Temperature Options  Speeds ranging from 5ns to 25ns  Power as low as 37mA at 25MHz  Commercial and Industrial versions available

Contextual Info: INC. PEEL 20CG10-25 CMOS Programmable Electrically Erasable Logic Device Features • Advanced CMOS EEPROM Technology ■ Architectural Flexibility — 92 product term X 44 input AND array — Up to 22 inputs and 10 outputs — Independently programmable

Contextual Info: Commercial/Industrial PA7572 PEEL Array Programmable Electrically Erasable Logic Array CMOS Electrically Erasable Technology - Reprogrammable in 40-pin DIP, 44-pin PLCC and TQFP packages Versatile Logic Array Architecture - 24 I/Os, 14 inputs, 60 registers/latches