PEEL18CV8S-7 Search Results
PEEL18CV8S-7 Datasheets (5)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
|---|---|---|---|---|---|---|---|
| PEEL18CV8S-7 |
|
-0.5 to 6.0 V, speed 7.5 ns tpd CMOS programmable electrically erasable logic device | Original | 203.91KB | 10 | ||
| PEEL18CV8S-7 |
|
CMOS Programmable Electrically Erasable Logic Device | Original | 647.34KB | 9 | ||
| PEEL18CV8S-7 | Integrated Circuit Technology | SPLD, PEEL18CV8 Family, EECMOS Process, 36 Gates, 12 Macro Cells, 8 Reg., 8 User I/Os, 5V Supply Voltage, 7.5 Speed Grade, 20-SOIC | Original | 321.81KB | 10 | ||
| PEEL18CV8S-7 | Unknown | CMOS Programmable Electrically Erasable Logic Device | Original | 335.9KB | 10 | ||
| PEEL18CV8S-7L |
|
CMOS Programmable Electrically Erasable Logic Device | Original | 647.34KB | 9 |