PECL10 Search Results

Q20P010

Abstract: Q20M100 carry look ahead adder Q20080 Q20P025 Q20025 vernier Q20000 Q20004 Q20010
Contextual Info: D EV IC E SP EC IFIC A TIO N LOGIC ARRAYS Q20000 “TURBO” ECL/TTL Q20000 FEATURES Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 10OK ECL and mixed ECL/TTL capability

Contextual Info: Product Specification Sheet April 1995 H^AlfcT Microelectronics Inital Use 1 2 0 1 A Cross Point Switch FT2000 Description This device is a Cross Point Switch device which operates at a maximum clock frequency of 155.52 MHz and a maximum data rate of 155.52 Mbits/s. The data is a scrambled NRZ format.

XTD22

Contextual Info: AT&T Microelectronics Product Specification Sheet 1042BL initial Use 5ESS EDC32 Description The 1042BL EDC32 performs error detection and correction on a 32-bit data word using seven bits of correction code. The correction code generated by the device is a modified Hamming

20STEP

Contextual Info: RHOMBUS I N D U S T R I E S 27E » IN C 7724120 0000141 • 1 ■ 10K & 100K ECL BUFFERED DELAY MODULES 3-BIT 10K ECL PROGRAMMABLE THROUGH-HOLE DIL. PECL3-XX SERIES PART NUMBER PECL3-.5 PECL3-1 PECL3-2 PECL3-3 PECL3-4 PECL3-5 PECL3-6

Contextual Info: RHOMBUS IN D U S T R IE S INC 45E » IRHB 7 7 B IH 2 0 0000253 1 10K & 100K ECL BUFFERED DELAY MODULES r-V7-/7 3-BIT 10K ECL PROGRAMMABLE THROUGH -HOLE D IL STEP Mn. Max. Max. ns (IW) D«v. (m DELAY (ns) PART NUMBER PECL3-0.5 PECL3-1 PECL3-2 P EC LM PECL3-4

carry look ahead adder

Abstract: Q20010 Q20120 Q20000
Contextual Info: DEVICE SPECIFICATION LOGIC A R R A Y S 020000 Q20000 FEATURES T U R B O ” ECL/TTL Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 100KECL and mixed ECL/TTL capability

Contextual Info: AT&T Product Specification Sheet Microelectronics 1055L Initial Use DDM2000 Virtual Tributary Pointer Processor Description 74 The 1055L Virtual Tributary Pointer Processor VIPPR is designed for DDM-2000 and DACS-2000 applications. The receive side of the VIPPR performs both STS-1 and VT1.5 pointer

Contextual Info: fax id: 5017 P Y p D jr q q CY7B9234 CY7B9334 PRELIM INARY x««* JL Jk IL LJL-i k«/ k»? SMPTE HOTLink Transmitter/Receiver Features bler/Framer Controller CY7C9335 completing the four piece chipset to transfer uncompressed SMPTE-259M encoded data over high-speed serial links (fiber, coax, and twisted pair).

Contextual Info: CY7B923 CY7B933 HOTLink Transmitter/Receiver Features twisted pair . Standard HOTLink data rates range from 160-330 Mbits/second. Higher speed HOTLink is also avail­ able for high speed applications 160-400 Mbits/second), as well as for those Low Cost applications HOTLink-155 (150-160

Contextual Info: AT&T Product Specification Sheet Microelectronics 1055N Initial U se NUT 5ESS Description 74 54 The 1055N NLIT is a custom device developed for use in the network link interface NU , electrical network link interface (ELI), and peripheral link interface (PU) paddleboards in the 5 E S S

Contextual Info: J iA T s J Product Specification Sheet Microelectronics Initial Use 1042BG 5ESS/5E8 Quad Z-Line Controller Description 60 44 10 26 The 1042BG Quad Z-Line Controller, Version 3 QZLC3 is used on the Z-interface pack of the ISLU2 to control four Z-line interface circuits. The QZLC3 interfaces between a 4 Mbits/s

Contextual Info: Electrical Specifications at 25°C Delay Max. Deviation Output Delay ns per Program Setting (P3*P2*P1) per Step ref. to Part Number (ns) (ns) no 4 4.5 5 ±.30 PECL3-0.5 0.5 ±.25 3 ±.30 3.5 5.5 6.5 4 ±.50 PECL3-1 ±.40 3 ±.30 5 7 9 PECL3-1.5 1.5 ±.50

Contextual Info: RHOriBUS INDUSTRIES INC hlZ D • 77P4TEn OOOGMBE 423 ■ RHB PECL Series 4-Bit Programmable 10K ECL Delays G EN E R AL: For Operating Specifications and Test Conditions, see Tables I and VII on page 8 of this catalog. Delays specified for the Leading Edge.

Contextual Info: GENERAL: For Operating Specifications and Test Conditions, see Tables IV and VIII on page 7 of this catalog. Delays specified for the Leading Edge. 10K ECL Buffered I/O 4-Bit Programmable Delay Modules Minimum Input Pulse W idth. 30% max. Delay