OX42 Search Results

USi ATTiny2313

Abstract: avr adc assembler code example
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

Contextual Info: Features • High Performance, Low Power AVR 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

Atmel ATTINY2313

Abstract: Application Note ATTINY2313 ATtiny2313 ATtiny2313-20PU ATtiny2313-20MU CS01 CS02 CS12 attiny2313-20pi DDD0
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

basic stamp BS2

Abstract: transistor z14 smd AC motor driver circuit using AVR DIAGRAM AVR GENERATOR single CHIP ac motor speed control atmel transistor smd ZH digital code lock schematic diagram SMD resistors R27 ATtiny2313 example design
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

ATtiny2313-20PU

Abstract: Atmel ATTINY2313 ATtiny2313 ATtiny2313-20SU ATtiny2313V-10PU Application Note ATTINY2313 ATTINY2313-20MU ATtiny2313V-10PU datasheet ATtiny2313V-10SU avr enhanced risc microcontroller data book
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

Ox42

Abstract: Atmel ATTINY2313 CS01 CS02 CS12 ATMEL ATTINY2313V-10PI
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

ba1513

Abstract: AT75C310 PA10 XC-01 Siapi
Contextual Info: Features ARM7TDMI ARM Thumb® Processor Core Two 16-bit Fixed-point OakDSPCore® Cores 256 x 32-bit Boot ROM 88K Bytes of Integrated Fast RAM for Each DSP Flexible External Bus Interface with Programmable Chip Selects Dual Codec Interface Multi-level Priority, Individually Maskable, Vectored Interrupt Controller

Contextual Info: Data Sheet January 1997 m i c r o e l e c t r o n i c s group Lucent Technologies Bell Labs Innovations T7901 ISA Single Wide Area Connection ISA-SWAC Device Features • Memory-based interrupt queue and command queue. ■ One wide area connection port that can be config­

attiny2313a

Abstract: ATTINY2313A-PU attiny4313 ATTINY2313A-SU RAM 4313 ATtiny4313-SU T2313 ATTINY4313-PU
Contextual Info: Features • High Performance, Low Power AVR 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

ATtiny2313V-8PJ

Abstract: ATtiny2313 Atmel ATTINY2313 SP-7
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

Tiny2313

Abstract: Atmel ATTINY2313 ATtiny2313 4Mhz DIAGRAM AVR GENERATOR 2543L
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

DIAGRAM AVR GENERATOR

Abstract: ATtiny2313-20PU smd zh AC motor driver circuit using AVR ATtiny2313-20SU AVR Hardware Design Considerations Features 4-bit even parity checker circuit diagram Atmel ATTINY2313 ATtiny2313 4Mhz basic stamp BS2
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

qml-38535

Abstract: MICROCIRCUIT ASIC
Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED REV SHEET REV SHEET 15 16 17 REV STATUS 18 19 20 21 22 23 24 25 26 26 27 1 2 3 4 5 6 7 8 REV OF SHEETS SHEET PMIC N/A PREPARED BY 9 10 11 12 13 Phu H. Nguyen STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS

Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

WGM12

Abstract: Atmel ATTINY2313 attiny2313 ATtiny2313-16MJ
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

ATtiny2313-20PU

Abstract: ATtiny2313V-10PU Application Note ATTINY2313 USi ATTiny2313 ATTINY2313-20SUR CS01 CS02 CS12 2543B-09 attiny2313
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

ATtiny2313-20PU

Abstract: CS01 CS02 CS12 ATtiny2313-20SU RXB8
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

ATtiny2313 4Mhz

Abstract: Atmel ATTINY2313
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

attiny2313a

Abstract: ATtiny2313 ATtiny2313 4Mhz
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

ATtiny2313-20SU

Abstract: Atmel ATTINY2313 ATTINY2313-20PU ATtiny2313 20SU CS01 CS02 CS12 Application Note ATTINY2313 attiny2313 ATTINY2313V
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

ATtiny2313-20PU

Abstract: ATtiny2313 CS01 CS02 CS12 Application Note ATTINY2313
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

ATtiny2313 4Mhz

Abstract: AC motor driver circuit using AVR basic stamp BS2 DIAGRAM AVR GENERATOR transistor z14 smd ATTINY2313 avr generator sei smd resistors single CHIP ac motor speed control atmel transistor 6 pin SMD Z2
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation