OTU1 Search Results

ODU0 to ODU2

Abstract: MXP2 HD-SDI over sdh OTU-2 OTU1 ODTU12 ROADM ODTU01 sfi4.1 stm 4 muxponder
Contextual Info: MXP2 10 Gb/s OTN Mapper and Multiplexer Highly Integrated Multiplexer and Mapper Features • • • • • • • • Supported by Exar’s comprehensive line of robust, integrated software solutions OTN Termination • OTU2/OTU1 overhead termination •

QSH-030-01-L-D-A

Abstract: QTH-030-01-L-D-A QSH-030-01-LD-A GR-253 OC48 V23816-N1018-C352 V23816-N1018-L352 QTH-030 samtec QTH-030-01-L-D-A
Contextual Info: V23816-N1018-C352/L352 * 3.3 V, 4-Line LVDS Parallel 2.7 GBd Transponder OC-48 OTU1 FEC SONET/SDH Short Reach (SR) up to 2 km Preliminary Dimensions in mm [inches] V23816-N1018-L352 • • • • • • • Loss of lock indicator for TX high speed clock

QSH-030-01-L-D-A

Abstract: QTH-030-01-L-D-A dfb laser diode oc-48 V23816-N1018-L362 GR-253 OC48 V23816-N1018-C362 OPTO-ISOLATOR
Contextual Info: V23816-N1018-C362/L362 * 3.3 V, 4-Line LVDS Parallel 2.7 GBd Transponder OC-48 OTU1 FEC SONET/SDH Intermediate Reach (IR-1) up to 15 km Preliminary Dimensions in mm [inches] V23816-N1018-L362 • • • • • • • Loss of lock indicator for TX high speed clock

OTU1

Abstract: EP4S100G5H40I1N Reed-Solomon Decoder FPGA
Contextual Info: G.709 FEC IP Core DS-1035 Data Sheet The Altera G.709 Forward Error Correction G.709 FEC IP core demonstrates the International Telecommunication Union-Telecommunication Standardization Sector (ITU-T) G.709 application of the Reed-Solomon (RS) algorithm in Optical Transport

UG366

Abstract: XC6VLX75T-FF784 aurora GTX XC6VLX240T-FF1759 verilog code of prbs pattern generator XC6VLX130T-FF784 XC6VSX475T-FF XC6VLX240T-FF784 XC6VLX130T FF1156
Contextual Info: Virtex-6 FPGA GTX Transceivers User Guide UG366 v2.2 February 23, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

s19235

Abstract: OC192C S19231PBI Generic AIS
Contextual Info: RUBICON-Metro ADVANCE Product Brief Part Number S19231PBI, Revision 1.2, October 2003 OC-192/48/12/3 DW/FEC/PM and ASYNC Mapper Device FEATURES G.709 ODU - 2 Synchronous and Asynchronous mapping “Right Sized” Transport of 10GE-LAN signals through OTN Network

CEI11

Abstract: PRBS11 UG371 XC6VHX255T-FF1155 FPGA Virtex 6 Ethernet h8440 PRBS31 DSP48E1 FF1155 FF1923
Contextual Info: Virtex-6 FPGA GTH Transceivers User Guide UG371 v2.0 February 16, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or

Contextual Info: CY7B991 CY7B992 PRELIMINARY CYPRESS SEMICONDUCTOR Programmable Skew Clock Buffer PSCB Features Functional Description • Output pair skew < 100 ps typical (250 max.) • All outputs skew <250 ps typical (500 max.) • 3.75- to 80-MHz output operation • User-selectable output functions

s19235

Abstract: OTU1 Motorola LH 6055 S3394 S19227PBI Gbps S19227PBI-2 OC192C OTN SWITCH rubicon
Contextual Info: RUBICON-LH Product Brief 10GE & OC192/48/12/3 DW/FEC/PM and AsyncMap Device with Strong FEC Part Number S19227PBI-2 Revision 1.0, March 2006 FEATURES • Minimal effort and maximum benefit upgrade path from original DispersionXX NIAGARA and S3094 solution.

prbs pattern generator

Abstract: OTU2 framer s19203 S19203CBI20 S19203CBI MPC860 S3091 S3092 OTU1
Contextual Info: HUDSON 2.0 Product Brief Part Number S19203CBI20, Revision 1.3, May 2003 Variable Rate Digital Wrapper Framer/Deframer, PM, and FEC Device The Hudson is a fully integrated, Variable Rate Digital Wrapper Framer/Deframer, Performance Monitor, and Forward Error Correction FEC

QSFP

Abstract: MPLS over optical packet switching OTU1 PDH/SDH stm 4 muxponder ethernet over sdh QSFP 40G transceiver stm 16 muxponder STM-16 Architecture ethernet over pdh
Contextual Info: Optical Transport Networks for 100G Implementation in FPGAs WP-01115-1.1 White Paper Based on announcements from vendors, enterprises and service providers, 100G system deployment is finally gaining real traction in the marketplace. The primary driver for this deployment is the customers’ ceaseless demand for higher bandwidth.

S4884

Abstract: OTU1 amcc CDR cpri CPRI multi rate
Contextual Info: PRODUC T BRIEF 8 S4 84 S4884 SONET/SDH/FC/GbE/HD-SDI Multi Rate Transceiver Features Description • Single reference clock for 13 different data rates ranging from 10 Mbps to 2.7Gbps programmable by hardware pins or by registers . • Frame / Boundary Detection and Byte

CPRI CDR

Abstract: Parallel Interfaces amcc CDR OTU1 cpri S4883 mapper
Contextual Info: PRODUC T BRIEF 3 88 S4 S4883 10 Mbps - 2.7 Gbps Continuous Rate Transceiver Features Description • Single reference clock for 10 Mbps - 2.7 The S4883 transceiver device is a fully integrated CMOS transceiver utilizing a single fixed rate reference clock for continuous rate

Contextual Info: 19-5270; Rev 1; 5/10 EVALUATION KIT AVAILABLE MAX3638 Evaluation Kit The MAX3638 evaluation kit EV kit is a fully assembled and tested demonstration board that simplifies evaluation of the MAX3638 low-jitter, wide-frequency range clock generator. The EV kit includes an on-board 25MHz

OTU1

Abstract: XIP2174 Paxonet Communications OC48 ISE4 OTN testbench
Contextual Info: STS48 OTN Framer/Digital Wrapper CC381 July 9, 2002 Product Specification AllianceCORE Facts Provided with Core Documentation User Guide, Design Guide EDIF netlist Design File Formats Constraints File cc381.ucf Testbench, test scripts Verification Tool

DS31408GN

Contextual Info: ABRIDGED DATA SHEET 19-5659; Rev 2; 2/11 DS31408 8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock General Description The DS31408 is a flexible, high-performance timing IC for diverse frequency conversion and frequency synthesis applications. On each of its eight input clocks

10G BERT

Abstract: circuit diagram of rf transmitter and receiver HD-SDI over sdh SDH 209 remote control transmitter and receiver circuit 5 channel RF transmitter and Receiver circuit CDR 211 AC circuit diagram of PPM transmitter and receiver circuit diagram video transmitter and receiver core i3 mother board circuit
Contextual Info: Stratix IV Device Handbook Volume 2 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V2-4.1 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

lm product

Abstract: ge 5040
Contextual Info: NEWS RELEASE The Connor-Winfield Corporation 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 | Fax: 630- 851- 5040 For Immediate Release Contact: August 2009 Ray Kepka 630.851.4722, x 4224 New 5x7mm LVDS and LVPECL Clocks from Connor-Winfield

VSC8664

Abstract: VSC8240 VSC8658 VSC3441 vsc7501 VSC8479 VSC8228 VSC7390 vsc8479-01 vsc7967
Contextual Info: Solutions Guide 2009 Vitesse means speed Innovation. Technical excellence. What it all comes down to is speed. Breaking records for the best performance, fastest data rates, highest integration, and lowest power, Vitesse is the only IC provider that has the proven technical expertise

Contextual Info: HMC1034LP6GE v01.0312 Clock Genertors - SMT CLOCK GENERATOR WITH FRACTIONAL-N PLL & INTEGRATED VCO, 125 - 3000 MHz 1 Typical Applications Features • 10G/40G/100G Optical Modules, Transponders, Line Cards Frequency Range: 125 - 3000 MHz • OTN and SONET/SDH Applications

Contextual Info: Short Form Data Sheet April 2012 MAX24305, MAX24310 5- or 10-Output Any-Rate Timing ICs with Internal EEPROM General Description The MAX24305 and MAX24310 are flexible, highperformance timing and clock synthesizer ICs that include a DPLL and two independent APLLs. When

tsmc design rule 40-nm

Contextual Info: Stratix IV Device Handbook Volume 1 Stratix IV Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V1-4.2 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.

Frequency Generator 1MHz

Abstract: MAX3639 60Ghz 37324
Contextual Info: 19-4911; Rev 0; 10/09 TION KIT EVALUA BLE IL AVA A Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs The MAX3639 is a highly flexible, precision phaselocked loop PLL clock generator optimized for the next generation of network equipment that demands low-jitter

Contextual Info: HMC1034LP6GE v02.0912 CloCk Generators - sMt CLOCK GENERATOR WITH FRACTIONAL-N PLL & INTEGRATED VCO, 125 - 3000 MHz 1 Typical Applications Features • 10G/40G/100G optical Modules, transponders, line Cards Frequency range: 125 - 3000 MHz • otn and sonet/sDH applications