OPT15 Search Results

Contextual Info: User’s Guide September 2012 SD3GDAIII User’s Guide 9/20/2012 SD3GDA III User’s Guide Lit#SNLU112 September 2012 Contents 1 INTRODUCTION . 1 2 SETUP . 2

Contextual Info: STM8AF6x26/4x/66/68 Automotive 8-bit MCU, with up to 32 Kbytes Flash, data EEPROM, 10-bit ADC, timers, LIN, SPI, I2C, 3 to 5.5 V Datasheet - production data Features • Core – Max fCPU: 16 MHz – Advanced STM8A core with Harvard architecture and 3-stage pipeline

Contextual Info: 1X9 Fiber Optic Transceiver for Fast Ethernet, FDDI, 155Mbps ATM FEA TU RES •F u ll c o m p lia n t w ith all m a jo r s ta n d a rd •M u ltis o u rc e d 1x9 p a c k a g e sty le w ith S T re c e p ta c le •F o r d is ta n c e o f u p to 2 k m •S in g le + 3 .3 V p o w e r su p p ly

OPT2702

Abstract: 60N01 E0C6001 E0C6002 PC-9800 S1C60N08 2-digit object counter circuit
Contextual Info: MF1192-02 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S5U1C60N08D Manual Development Software Tool for S1C60N08 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any

epson c90

Abstract: 60N01 E0C6001 E0C6002 E0C6003 E0C6004 PC-9800 printer epson c90
Contextual Info: MF863-04 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S5U1C6S3N2D Manual Development Software Tool for S1C6S3N2 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any

STM8A

Abstract: STM8AF62xx H6166 STM8af6266 MA6491 pm0044 sda 5241 STM8 CPU programming manual STM8S 5401 DM
Contextual Info: STM8AF622x/4x STM8AF6266/68 STM8AF612x/4x STM8AF6166/68 Automotive 8-bit MCU, with up to 32 Kbytes Flash, data EEPROM, 10-bit ADC, timers, LIN, SPI, I2C, 3 to 5.5 V Features • Core – Max fCPU: 16 MHz – Advanced STM8A core with Harvard architecture and 3-stage pipeline

OPT-155B

Contextual Info: OPT-155Bxxxx 155Mbps 1x9 SC Duplex Optical Transceiver Module for Fast Ethernet, ATM, SONET/SDH STM-1/OC-3 Features： Full Compliance with the Optical Performance Requirements of the ATM 100Mbps and 100 Base-FX Version of IEEE 802.3u. Industry Standard 1x9 Footprint and Duplex

NEC 05F specification

Abstract: NEC 05F NEC uPA 63 H nec o5f PD4094 D6122G PD6121 ks-49 pd4094b pj 0266 iv
Contextual Info: ï r — -S? ♦ S' — h S S J _ M O S *if« IIl£ & SVIO S In tegrateci Circuit uPD17012 G F -071 • X - r U ^ - [ È ] ( t F M , A M ( M W , L W , 7“U ^ - 7 5 P L L Ü 5 m v > ir ^ 'f if 5 LC D =3> 4 f c f 'y

HFBR-5903

Abstract: HFBR-5103 LXT971A 100BASE-FX LXT973 MC100LVEL92 application of HFBR-5103 OPT-155A2H1
Contextual Info: Intel 100BASE-FX Fiber Optic Transceivers: Connecting a PECL/LVPECL Interface Application Note April 2003 Document Number: 250781 Revision Number: 001 Revision Date: April 10, 2003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

um0470

Abstract: pwm module stm8 H617 PM0047 UM0500 STM8AH61x PURE 5001h H5178
Contextual Info: STM8AF61xx, STM8AH61xx STM8AF51xx, STM8AH51xx Automotive 8-bit MCU, with up to 128 Kbytes Flash, EEPROM, 10-bit ADC, timers, LIN, CAN, USART, SPI, I2C, 3 V to 5.5 V Features Core • Max fCPU: 24 MHz ■ Advanced STM8A core with Harvard architecture and 3-stage pipeline

ST72321M9

Abstract: TQFP64 footprint
Contextual Info: ST72321M/R/AR 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE PRODUCT PREVIEW • ■ ■ ■ ■ Memories – 32K to 60K dual voltage High Density Flash HDFlash or ROM with read-out protection capability. In-Application Programming and

IC403

Contextual Info: ST72321J 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 5 TIMERS, SPI, SCI, I2C INTERFACE PRODUCT PREVIEW • ■ ■ ■ ■ Memories – 48 to 60K dual voltage High Density Flash HDFlash or ROM with read-out protection capability. In-Application Programming and

ST72321M9

Contextual Info: ST72321M/R/AR 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE PRODUCT PREVIEW • ■ ■ ■ ■ Memories – 16K to 60K dual voltage High Density Flash HDFlash or ROM with read-out protection capability. In-Application Programming and

communication transmitter and receiver circuit diagram

Abstract: 1310nm TRANSMITTER CIRCUIT DIAGRAM transceiver LED PIN 155mbps
Contextual Info: OPT-155Axxxx 155Mbps 1x9 SC/ST Duplex Optical Transceiver Module for Fast Ethernet, ATM, SONET/SDH STM-1/OC-3 Features： Full Compliance with the Optical Performance Requirements of the ATM 100Mbps and 100 Base-FX Version of IEEE 802.3u. Industry Standard 1x9 Footprint and Duplex

S-7760A

Abstract: WLP-16
Contextual Info: S-7760A Series www.sii-ic.com PROGRAMMABLE PORT CONTROLLER PORT EXPANDER WITH BUILT-IN E2PROM CIRCUIT Rev.2.0_00 Seiko Instruments Inc., 2007-2010 The S-7760A is a programmable port controller IC comprised of an E2PROM, a control circuit for data output, a circuit to

bz ae1

Abstract: lcd cross reference epson printer board stepping motor EPSON epson cb report 2-digit object counter circuit 9a3 diode hex to 7 segment decoder moving message display using 7 segment 60N01
Contextual Info: MF882-03 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S5U1C6S2N7D Manual Development Software Tool for S1C6S2N7 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any

Contextual Info: OPT-155Bxxxx 155Mbps 1x9 SC Duplex Optical Transceiver Module for Fast Ethernet, ATM, SONET/SDH STM-1/OC-3 Features： Full Compliance with the Optical Performance Requirements of the ATM 100Mbps and 100 Base-LX Version of IEEE 802.3u. Industry Standard 1x9 Footprint and Duplex

322267

Abstract: MX93111 IPT84 MX93111 FC MX93011C
Contextual Info: MX93111 MX93111 DATA SHEET CONTENT 1 INTRODUCTION 1.1 FEATURE 1.2 DIFFERENCE BETWEEN MX93011C AND MX93111 2 3 2 PIN 2.1 2.2 2.3 2.4 2.5 PIN OUT FOR 128 PIN PQFP MX93111 PIN DESCRIPTIONS PIN TYPE ABBREVIATION PINS SUMMARY BY PIN TYPE MULTIPLEX PINS 4 6 9 9

R50032471

Contextual Info: OPT-155Bxxxx 155Mbps 1x9 SC Duplex Optical Transceiver Module for Fast Ethernet, ATM, SONET/SDH STM-1/OC-3 Features： z Full Compliance with the Optical Performance Requirements of the ATM 100Mbps and 100 Base-LX Version of IEEE 802.3u. z Industry Standard 1x9 Footprint and Duplex

Contextual Info: OPT-155Bxxxxxx 155Mbps 1x9 SC Duplex Optical Transceiver Module for Fast Ethernet, ATM, SONET/OC-3, SDH/STM-1 Features： Full Compliance with the Optical Performance Requirements of the ATM 100Mbps and 100 Base-FX Version of IEEE 802.3u. Industry Standard 1x9 Footprint and Duplex

EAD0-EAD14

Abstract: ED11 ED12 ED13 ED15 MX93011A 89 04c2
Contextual Info: INDEX MX93011A APPLICATION NOTE [K1 VERSION] 1.0 GENERAL DESCRIPTIONS l l l MX93011A is an engine chip for digital answering machine DAM . It provides functional modules, including speech compression/decompression, silence management, telephone line signal processing, internal-ROM voice prompt, ARAM management, etc.

4D00H

Abstract: ED11 ED12 ED13 ED15 MX93031A
Contextual Info: INDEX PRELIMINARY MX93031A APPLICATION NOTE [K1 VERSION] 1.0 GENERAL DESCRIPTIONS l l l The MX93031A is an engine chip on which digital answering machine DAM with full duplex speakerphone is implemented. Besides, CAS tone detection capability for call-waiting in Caller-ID service has also been

Contextual Info: STM8AF5xxx STM8AF6x69/7x/8x/9x/Ax Automotive 8-bit MCU, with up to 128 Kbytes Flash, data EEPROM, 10-bit ADC, timers, LIN, CAN, USART, SPI, I2C, 3 to 5.5 V Datasheet - production data Features • Core – Max fCPU: 24 MHz – Advanced STM8A core with Harvard

fc-638l

Abstract: GTS FC-638L fc-638 FC638L 40ST1041AX H1164 RTL8208 100base AA100 AA111
Contextual Info: RTL8208 REALTEK SINGLE CHIP OCTAL 10/100 MBPS FAST ETHERNET TRANSCEIVER RTL8208 7.4.2 Receive Function . 21 7.4.3 Link Monitor . 22 7.4.4 Baseline Wander Compensation . 23