OPERATE Search Results

Contextual Info: SN75LBC241 LOW-POWER LinBiCMOS MULTIPLE DRIVERS AND RECEIVERS SLLS137E - MAY 1992 - REVISED JANUARY 1999 • Operates With Single 5-V Power Supply • Meets or Exceeds the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 • Improved Performance Replacement for

2SD1294

Contextual Info: SILICON NPN TRIPLE DIFFUSED TYPE PCT PROCESS 2SD1294 POWER REGULATOR FOR LINE OPERATED TV. Unit in mm # 3 .2 ± Q 2 FEATURES : . Excellent Wide Safe Operating Area (80 W.s z at Tc=25°C) . eo . Included Abalanche Diode : Vz=60±15V . High DC Current Gain

Contextual Info: TC55417P/J —15H. TC55417P/J-20H TC55417P/J—25H. TC55417P/J-35H • * 16,384 W O R D x 4 BIT CMOS STATIC RAM DESCRIPTION The TC55417P/J—H is a 65,536 bit high speed static random access memory organized as 16,384 words by 4 bits using CMOS technology, and operated from a single 5 - volt supply.

S1854

Abstract: transistor s1854 s1854 a s1854 equivalent ic s1854 SI854 REGULATOR s1854 transistor s1854 ic error REGULATOR IC FOR 150V s1854 B1036
Contextual Info: SILICON N-SUBSTRATE MONOLITHIC TYPE S1854 SI854 IS A REGULATOR DRIVER FOR LINE OPERATED TV, Unit in mm WHICH ARE BUILT UP OF ERROR AMPLIFIER TRANSISTOR, 10.3MAX. 0&6±O,2 STANDARD VOLTAGE ZENER DIODE AND POLY-SILICON RESISTORS ON MONOLITHIC CHIP. FEATURES:

260-pin

Contextual Info: TOSHIBA TC55V1864J/FT-10/12/15 PRELIMINARY SILICON GATE CMOS 65,536 WORD x 18 BIT CMOS STATIC RAM Description TheTC55V1864J/FT is a 1,179,648 bit high speed CMOS static random access memory organized as 65,536 words by 18 bits and operated from a single 3.3V : upply. Toshiba’s advanced CMOS technology and circuit design enable high speed operation.

Contextual Info: AM26LS31C QUADRUPLE DIFFERENTIAL LINE DRIVER _D 2433. JA N U A R Y 19 7 9 -R E V IS E D M AY 1990 Meets EIA Standard RS-422-A D, J, OR N PAC KAG E TOP V IE W Operates From a Single 5-V Supply 1Y [ 2 16 ] V C C 15 ] 4 A 1Z[ ENABLE G [

Contextual Info: T O SH IB A TA6009FN TO SH IBA BIPO LAR LINEAR INTEGRATED CIRCUIT SILICON M ONOLITHIC TA6009FN SHOCK SENSOR IC Ich VERSION TA6009FN detects an existence o f external shock through t h p <;hnrk i p n i n r a n d n i i t n u t FEATURES • TA6009FN operates from 2.7 ~5.5 V DC single power

Contextual Info: INTRODUCTION Today's portable and battery-operated system designer is faced w ith the problem of keeping ahead when addressing system perform ance, long battery life, in terfacin g te ch n o lo gy, and reliability. Toshiba's low vo lta g e high perform ance C2MOS logic fam ilies help designers achieve these goals.

lt928

Abstract: 55328P TC55328J
Contextual Info: 3 2 ,7 6 8 W O R D x 8 B IT C M O S S TA TIC R A M D E S C R IP T IO N The TC55328P/J is a 262,144 bits high speed static random access memory organized as 32,768 words by 8 bits using CMOS technology, and operated from a single 5-volt supply. Toshiba's CMOS

Contextual Info: D • f SN75124 TRIPLE LINE RECEIVER 0*^1.724 0005531 3 I TXI4 TEXAS INSTR L I N / I N T F C D 1 32 2 , SEPTEMBER 1973-BE V ISE D SEPTEMBER 1989 Meets IBM System 3 6 0 Input/Output Interface Specifications D, J, OR N PACKAGE (TOP VIEW) Operates from Single 5-V Supply

TDC1005

Abstract: TRW LSI Products
Contextual Info: TDC1005 T ir lfV Serial Shift Register Dual 64-Bit • • • • • The TRW TD C1005 is a dual 64-bit positive-edgetriggered serial shift register which operates at 25M Hz. This device is cascadable in the number of words and the word size. Complementary TTL outputs Q and Q

Contextual Info: TOSHIBA TC55V1664J/FT-10/12/15 PRELIMINARY SILICON GATE CMOS 65,536 WORD x 16 BIT CMOS STATIC RAM Description The TC55V1664J/FT is a 1,048.5,'6 bit high speed CMOS static random access memory organized as 65,536 words by 16 bits and operated from a single 3.3V sjpply. Toshiba's advanced CMOS technology and circuit design enable high speed operation.

TCD131D

Abstract: TC74HC04P 2SA1015-Y 2SA1015 Y
Contextual Info: C D 1 3 1 D The TCD131D is a high resolution and high sensitivity 2048-element linear image sensor. The device can be used foi OCR» POS handscanner bar-code type , and other optical measurements. The device is operated by only 12V power supply. The device is mounted in 22-pin Cerdip package

LT114

Contextual Info: 01 31724 0 Q 8 3 0 Ô Û b TEXAS INSTR m (L I N / I N T F C m 'T 'lS r H S . '0 5 UA9638C DUAL HIGH-SPEED DIFFERENTIAL LINE DRIVER 40E D D2612, OCTOBER 19 80-R EV I5 60 SEPTEMBER 19B6 D, JQ , OR P PACKAGE • Meets EIA Standard RS-422-A • Operates From a Single 5-V Supply

912BI

Contextual Info: TOSHIBA NIOS MEMORY PRODUCTS TC55329P/J-20, TC55329P/J-25 TC55329P/J-35 DESCRIPTION The TC55329P/J is a 294,912 b i t s high speed s t a tic random access memory organ ized as 32,768 words by 9 b i t s using CMOS technolo gy, and operated from a s in g le 5 -v o lt supply.

Contextual Info: TL714C HIGH-SPEED DIFFERENTIAL COMPARATOR _ S L C S 0 15-D 3131, DECEMBER 1 9 8 8 - REVISED JUNE 1969 I * • • • • D OR P PACKAGE {TOP VIEW Operates From a 5-V Supply Self-Biasing Inputs Hysteresis. . . 10 mV Typ Response Time. . . 6 ns Typ

tsp5220

Abstract: tsp53c30 TSP50C41 tsp50c4x TSP50C30 TSP6100 53C30 wf7n TMS7000 development system TMS7000 data manual
Contextual Info: 1.0 INTRODUCTION The TSP53C30 Is a programmed TSP50C41 that operates as a slave device to a mlcroprocessor. The TSP53C30 Includes a 10 pole Linear Predictive Filter the synthesizer an 8K ROM and an 8-blt microprocessor. The speech synthesizer operates on Linear Predictive Code (LPC) or Pulse Code Modulated (PCM)

Contextual Info: y U IM IT R O D E UC161A UC161B UC161C • Direct CMOS Logic Compatibility • Low Power • Direct Wire-OR of Outputs The UC161 family of quad comparators feature programmable DC and AC parameters. A single external resistor can set the comparators to operate in the microwatt region for battery applications, or higher cur­

Contextual Info: TOSHIBA MOS MEMORY PRODUCTS TC55465P/J-20, TC55465P/J-25 TC55465P/J-35 ¡d e s c r ip t io n ] The TC55465P/J is a 262,144 b i t s high speed s t a t i c random ac c e ss memory organ ized as 65,536 words by 4 b i t s using CMOS tech n o lo g y , and operated from a s in g le 5 -v o lt supply.

Contextual Info: CDC351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SC AS339-FEBRU ARY 1994-R E V IS E D MARCH 1994 DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distributlon and Clock-Generation Applications Operates at 3.3 Vcc LVTTL-Compatlble Inputs and Outputs

2SD1092

Abstract: TCS5C
Contextual Info: 2SD1092 SILICON NPN TRIPLE DIFFUSED TYPE POWER REGULATOR FOR LINE OPERATED TV. Unit in m m 03.Z±O.2 FEATURES : . Excellent Wide 80 W . S e c Safe Operating Area at Tc=25°C . I n c l u d e d A b a l a n c h e Di o d e : . High DC Current Gain : h F E — 500

Contextual Info: TOSHIBA MOS MEMORY PRODOCTS TC55417P/J-15H, TC55417P/J-20H Id e s c r i p t i o h I The TC55417P/J is a 65,536 bit high speed static random access memory organized as 16,384 words by 4 bits using CMOS technology, and operated from a single 5-volt supply. Toshiba's high performance device technology provides both high speed and low power

Contextual Info: UÄ9638C DUAL HIGH-SPEED DIFFERENTIAL LINE DRIVER SLLS112C- OCTOBER 1980 - REVISED APRIL 1994 D OR P PACKAGE crop view Meets or Exceeds AN SI Standard EIA/TIA-422-B Operates From a Single 5-V Power Supply Vcct 1A[ 2 2A[ 3 GND [ 4 Drives Loads as Low as 50 Q up

TC55416P-20H

Contextual Info: TOSHIBA MOS MEMORY PRODUCTS TC55416P-15H, TC55416P-20H ¡d e s c r i p t i o n ] The TC55416P/J is a 65,536 bit high speed static random access memory organized as 16,384 words by 4 bits using CMOS technology, and operated from a single 5-volt supply, Toshiba's high performance device technology provides both high speed and low power