OC 1016 Search Results

oak technology oti 067

Abstract: oak oti-067 P2WKP
Contextual Info: DC SPECIFICATION ABSOLUTE MAXIMUM RATINGS Ambient Operating Temperature OC to +70C Storage Temperature -65 deg C to +150 deg C Supply Voltage to Ground Potential -0.5V to +7.0V Applied Input Voltage -0.5V to +7.0V Stresses above those listed may cause permanent damage to the device. These are

67164

Abstract: 0E12 UT67164 SRAM flatpack
Contextual Info: Standard Products UT67164 Radiation-Hardened 8K x 8 SRAM - SEU Hard Data Sheet December 1999 FEATURES q 55ns maximum address access time, single-event upset less than 1.0E-10 errors//bit day -55oC to 125+oC q Asynchronous operation for compatibility with industrystandard 8K x 8 SRAM

tefr1

Abstract: 0E12 UT67164
Contextual Info: Standard Products UT67164 Radiation-Hardened 8K x 8 SRAM - SEU Hard Data Sheet December 1997 FEATURES q 55ns maximum address access time, single-event upset less than 1.0E-10 errors//bit day -55oC to 125+oC q Asynchronous operation for compatibility with industrystandard 8K x 8 SRAM

Contextual Info: Standard Products UT67164 Radiation-Hardened 8K x 8 SRAM - SEU Hard Data Sheet December 1997 FEATURES q 55ns maximum address access time, single-event upset less than 1.0E-10 errors//bit day -55oC to 125+oC q Asynchronous operation for compatibility with industrystandard 8K x 8 SRAM

Contextual Info: 156 Mbps OPTICAL RECEIVER OD-J6503-HB01 FEATURES MAJOR PERFORMANCE • DESIGNED FOR SONET/SDH/ATM SYSTEMS • DATA RATE: 155.52 Mbps STM-1, OC-3 • REFLOW SOLDERABLE SMT PACKAGE • P-ECL SIGNAL LOGIC INTERFACE • COMPACT SIZE: 26 x 10 x 3 (mm) • ALARM FUNCTIONS:

GR-253-CORE

Contextual Info: OD-J6501-0A01 OD-J6501-HB01 156 Mbps OPTICAL RECEIVER FEATURES MAJOR PERFORMANCE • DESIGNED FOR SONET/SDH/ATM SYSTEMS • DATA RATE: 155.52 Mbps STM-1, OC-3 • REFLOW SOLDERABLE SMD HOUSING • P-ECL SIGNAL LOGIC INTERFACE • COMPACT SIZE: 26 x 10 x 3 (mm)

0E12

Abstract: UT67164
Contextual Info: Standard Products UT67164 Radiation-Hardened 8K x 8 SRAM - SEU Hard Data Sheet January 2002 FEATURES q 55ns maximum address access time, single-event upset less than 1.0E-10 errors//bit day -55o C to 125+oC q Asynchronous operation for compatibility with industrystandard 8K x 8 SRAM

Contextual Info: g THERMOCOUPLES: GENERAL INFORMATION Temperature measurement with thermocouples is based on measurement of electrical voltage. The output voltage emf of thermocouples, E, varies with the temperature in a predetermined fashion. The relationship between temperature t (oC) and emf E (mV) can be expressed by mathematical functions as follows:

pin diagram of mc68hc811e2

Abstract: 48-Pin DIP MC68HC811E2 1838 ir receiver 11E20 4800 FF adcb 27 MC68HC711 STK 5333 MC68S711E9 MC68HC11
Contextual Info: MC68HC11ERG/AD M68HC11E SERIES PROGRAMMING REFERENCE GUIDE M MOTOROLA Block Diagram PAI/OC 1 0C2/0C1 0C3/0C1 0C4/0C1 IC4/OC5/OC1 IC1 IC2 IC3 PA7/PAI/0C1 PA6/OC2/OC1 PA5/OC3/OC1 PA4/OC4/OC1 PA3/IC4/OC5/OC10 ) PA2/IC1 — > PA1/IC2— > PA0/IC3— >• PULSE ACCUMULATOR

8713B

Abstract: T648 B1193 T646
Contextual Info: SN54HCT646. SN54HCT648, SN74HCT646, SN74HCT648 OC TAL BUS TRAN SC EIVERS AN D REGISTERS WITH 3 S TA TE OUTPUTS D 2 8 0 4 , M AR C H 1 9 8 4 -R E V IS E D SEPTEMBER 1 9 8 7 • Inputs are TTL-Voltage Compatible • Independent Registers lor A and B Buses •

tca02

Abstract: AF-UNI-0010 0x513 concatenated and OC-3 and STM-1 ag20 tayio dfp 1016 TCA 105B CRC-16 CRC-32 GR-253-CORE
Contextual Info: 38 AM S/UNI -8x155 ASSP Telecom Standard Product Data Sheet Released da y, 14 Oc to S/UNI®-8x155 be r, 20 03 01 :0 4: PM5380 Data Sheet Released Issue No. 2: June 2002 lo ad ed by Am r Ma ns ou ro fS ilic on Ex pe rt Te cn ol og yI nc on Tu es SATURN® User Network Interface

transistor C3866

Abstract: Zener PH SEC E13009 ups circuit schematic diagram 1000w E13007 2 E13007 C3866 power transistor texas ttl 74L505 Transistor C3246
Contextual Info: BID CΚΤ DOLLY L IST L OGO LIST SA F E TY & RELIA ΒL TY ΤΕΚ PIN SYSTE M DIGITA L IC's MEMORIES, MOS CMOS .EC L , TT L MICR OP R OC E SSOR SPE CIA L FUN CTION IC's DIGITAL l LINE AR K ARR AYS LIN E A R IC's (PUR CH ) ΤΕΚ-MADE IC's IC's INDEX (COL ORE D PGS)

stk 412 -410

Abstract: IC stk 412 410 stk 142 150 C167SR-LM C166 C167 C167CR C167CR-16RM C167CR-4RM C167CR-LM
Contextual Info: U s er ’ s Ma n u al , V 3. 1 , M ar . 20 0 0 C167CR Derivatives 1 6- B i t S in gl e- C hi p M i cr oc o nt ro ll er Mi cro c on tr ol le rs N e v e r s t o p t h i n k i n g . Edition 2000-03 Published by Infineon Technologies AG, St.-Martin-Strasse 53,

MIL-M-38510 301

Abstract: ax 3003 1N3064 TT 46 N 16 LOF 13003J
Contextual Info: r MIL-M-38510/331A 4 November 1985 _ s i p m s m r f n i -MIL-M-38510/33HUSAF 26 J u n e 1 9 7 8 SPECIFICATION military MI CR OC IRC UI TS, DIGITAL, 3 IPOLAR ^OW-POMER FLIP-FLOPS, CASCAOABLE, MONOLITHIC T h i s s p e c i f i c a t i o n is a p p r o v e d f o r us e by al 1

ic 8086

Abstract: 616P
Contextual Info: 71 A±0.3C B ± 0 .15 Specificotions: o o o o o o o o o o o o OOOOOOOOOOOOOO N o t e l: With m iddle b c r 18 - 6 4 P} ^ÎlTTTTTTTTTTT? I I. 2.5»±0.10 PO.3 [I 1F I A+0.3C 3 C ir c u its D W .A DIM.B 6 7.62 1016 5.08 OIV.C 10.16 DIU.D 7.62 6 1-4 16 7.6 2

Pulse generator wiring diagram

Abstract: EMV-PG01L EMV-PG01X EMV-PG01O pg01o incremental encoder AWG16 AWG18 12v generator diagram 3 PHASE MOTOR line wiring diagram
Contextual Info: 2007-04-12 A. Y EMV-PG01O Wiring 1 jumper 2.1 Outline Braking resistor optional Non-fuse breaker 5011647401-EM01 http://www.delta.com.tw/industrialautomation/ R NFB S EMV-PG01 Instruction Sheet T REV/STOP Multi-step 1 Factory setting Multi-step 2 Multi-step 3

Contextual Info: 10 39170 92.4 16 POSITION SHOWN NO. OR DIM. M A T E R IA L CIRCUITS "A" NUMBER 14 50.8 [2.00] 39170-1014 16 53.3 [2.10] 39170-1016 20 61.0 [2.40] 39170-1020 26 76.2 [3.00] 39170-1026 34 95.0 [5.74] 59170-1034 40 111.5 [4.59] 59170-1040 50 135.6 [5.34] 39170-1050

l1113

Contextual Info: F 10168 • F 10568 F10K VOLTAGE COMPENSATED ECL QUAD LATCH/GATED OUTPUTS DESCRIPTION - The F10168 and F10568 contains four D type latches with a Common Enable Ec . When E c is HIGH, outputs will follow the D inputs. Information is latched on the negative-going edge of E c Each latch output is combined with a separate gate control (Gn),

FB 3306

Abstract: 7200L 18504 845 motherboard circuit 7804 inverter 7805 ACT 845 motherboard BTL 8 236 CMOS 4060 cmos open collector
Contextual Info: Section 2 Functional Index Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Inverting/Noninverting Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Buffers/Drivers and Bus Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

Contextual Info: Full Accurate 14/16 Bit Vout nanoDacTM, Buffered, 3V/5V, Sot 23 AD5040/AD5060 Preliminary Technical Data FEATURES Single 14/16-Bit DAC, 1 Lsb inl. Power-On-Reset to Zero Volts/Mid Scale Three Power-Down Functions Low Power Serial Interface with SchmittTriggered Inputs

AD5060BRJ-1REEL7

Abstract: AD5040 AD5060 AD5060BRJ-1 AD5061 AD5062 AD5063
Contextual Info: Full Accurate 14/16 Bit Vout nanoDacTM, Buffered, 3V/5V, Sot 23 AD5040/AD5060 Preliminary Technical Data FEATURES Single 14/16-Bit DAC, 1 Lsb inl. Power-On-Reset to Zero Volts/Mid Scale Three Power-Down Functions Low Power Serial Interface with SchmittTriggered Inputs

OC-106 94V0 C

Abstract: olin 7025 CDA 194 Tamac4 eftec 7025 alloy lead frame sn 8400 Au Sn eutectic thermal conductivity Eftec 64t
Contextual Info: 2 5 Physical Constants of IC Package Materials 1/16/97 3:41 PM CH05WIP.DOC INTEL CONFIDENTIAL until publication date 2 CHAPTER 5 PHYSICAL CONSTANTS OF IC PACKAGE MATERIALS The Table 5-1 through Table 5-5 list typical values for selected properties of materials used in

AD5060BRJ-2REEL7

Contextual Info: Full Accurate 14/16 Bit Vout nanoDacTM, Buffered, 3V/5V, Sot 23 AD5040/AD5060 Preliminary Technical Data FEATURES Single 14/16-Bit DAC, 1 Lsb inl. Power-On-Reset to Zero Volts/Mid Scale Three Power-Down Functions Low Power Serial Interface with SchmittTriggered Inputs

FB 3306

Abstract: pcf 817 CD4000 SERIES BOOK BR 8550 sn 16861 7 SEGMENT DISPLAY cd 4511 74 LS 00 Logic Gates pcf 9555 HC 40106 NXP 74LVC1G
Contextual Info: TM Technology for Innovators Logic Selection Guide 2007 2 ➔ Logic Selection Guide Texas Instruments Important Notice Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any