NON-PIPELINED SINGLE-CYCLE PROCESSOR Search Results

Contextual Info: MOTOROLA Freescale Semiconductor, Inc. Order this document by MCM63P631A/D SEMICONDUCTOR TECHNICAL DATA MCM63P631A Product Preview Freescale Semiconductor, Inc. 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM63P631A is a 2M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC, and Pentium microprocessors. It is organized as 64K words of 32 bits

MCM69F536C

Abstract: MCM69F536CTQ10 MCM69F536CTQ12 MCM69F536CTQ8 MCM69F536CTQ8R MCM69F536CTQ9 MCM69F536CTQ9R
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 32K x 36 Bit Flow–Through BurstRAM Synchronous Fast Static RAM The MCM69F536C is a 1M–bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC, 486, i960, and Pentium microprocessors. It is organized as 32K

MCM69P817

Abstract: MCM69P817ZP3 MCM69P817ZP3R
Contextual Info: MOTOROLA Order this document by MCM69P817/D SEMICONDUCTOR TECHNICAL DATA MCM69P817 Product Preview 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM69P817 is a 4M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC and other

Contextual Info: 0 M IF IR IfflM D @ R 9 in te i 82395DX HIGH PERFORMANCE SMART CACHE Optimized Intel386 DX Microprocessor Companion Concurrent Line Buffer Cacheing Multiprocessor Support Integrated 16KB Data RAM Expandable - up to 64KB 4 Way SET Associative with Pseudo

82395DX

Abstract: cr 5228 t intel 82395 82395 DMLF 164 weitek sd21, phi intel 82385 29038 weitek 3171
Contextual Info: in te i 82395DX HIGH PERFORMANCE SMART CACHE Optimized intel386TM DX Microprocessor Companion Concurrent Line Buffer Cacheing Integrated 16KB Data RAM Expandable - up to 64KB Supports lntel486TM Microprocessor­ like Burst Multiprocessor Support 4 Way SET Associative with Pseudo

Contextual Info: HY5216256 Series -HYUNDAI 256Kx 16-bit Video RAM with 2CAS Introduction Overview The 4megabit Video RAM is an application specific memory device designed for graphics applications. It comprises a 256k x16 DRAM memory array interfaced to a 256 x16 Serial Access Memory SAM , or register.

MCM69P818

Abstract: MCM69P818ZP4 MCM69P818ZP4R
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM69P818 is a 4M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. It is organized as 256K words of 18 bits

25P010

Contextual Info: o Preliminary W25P010A Mnbond Electronics Corp. 32K x 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM GENERAL DESCRIPTION The W 2 5 P 0 1 0 A is a high-speed, synchronous-burst-pipelined, low-power C M O S static RAM organized as 32 ,768 x 3 2 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address

MCM63P733A

Abstract: MCM63P733ATQ100 MCM63P733ATQ117 MCM63P733ATQ133 MCM63P733ATQ150 MCM63P733ATQ90 SCM63P733A SCM63P733ATQ133 motorola cmos scm
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM63P733A and SCM63P733A are 4M–bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache. The MCM63P733A and SCM63P733A organized as 128K words by 32 bits

80960CA

Abstract: Non-Pipelined Single-Cycle processor 80960CA-16 80960CA-25 270710
Contextual Info: SPECIAL ENVIRONMENT 80960CA-25 -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR  Two Instructions Clock Sustained Execution  Four 59 Mbytes s DMA Channels with Data Chaining  Demultiplexed 32-bit Burst Bus with Pipelining Y 32-bit Parallel Architecture Two Instructions clock Execution

Contextual Info: Intel 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Dem ultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two Instructions/clock Execution

MCM69P819

Abstract: MCM69P819TQ4 MCM69P819TQ4R MCM69P819ZP4 MCM69P819ZP4R
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM69P819 is a 4M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. It is organized as 256K words of 18 bits

Contextual Info: in te l SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining i • 32-bit Parallel Architecture

Contextual Info: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)

Contextual Info: intJ. 80960CA-33, -25, -16 32-BIT HIGH PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-Bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two instructions/clock Execution

Contextual Info: MOTOROLA Order this document by MCM63P737K/D SEMICONDUCTOR TECHNICAL DATA Advance Information 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM MCM63P737K MCM63P819K The MCM63P737K and MCM63P819K are 4M–bit synchronous fast static

ib17

Contextual Info: M D M M ! 0 M [F © [s ]ß M ? 0 © M SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining

FGT 313

Contextual Info: in te i ¡860 XR 64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for

Contextual Info: ADC12181 ADC12181 12-Bit, 10 MHz Self-Calibrating, Pipelined A/D Converter with Internal Sample & Hold Literature Number: SNAS040C ADC12181 12-Bit, 10 MHz Self-Calibrating, Pipelined A/D Converter with Internal Sample & Hold General Description The ADC12181 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit

Contextual Info: 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • • Two Instructions/Clock Sustained Execution Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two Instructions/clock Execution

Contextual Info: Ä P m K K g l 0 MF [F3[ifflAT0®[N] SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining

AN1704

Abstract: MCM69D536 MCM69D618 signal path designer
Contextual Info: MOTOROLA Order this document by AN1704/D SEMICONDUCTOR TECHNICAL DATA AN1704 Switch Fabric Implementation Using Shared Memory Prepared by: Lakshmi Mandyam and B. Kinney INTRODUCTION Whether it be for the World Wide Web or for an intra–office network, today’s businesses and services are heavily dependent on the telecommunications infrastructure. Computers

Contextual Info: intei 80960CF-33, -25,-16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining

G1251

Abstract: GE NPX intel 8295 Block diagram microprocessor 8097 architecture i386 ex 80287 coprocessor architecture i387 d1251 M8087 M80B
Contextual Info: SÖE D HÔ2bl7S 012S1Û1 4Ô5 • ITL1 INTEL CORP U P / P R P H L S MILITARY ¡387 MATH COPROCESSOR ' T ' i\(\-\Z -Q 5 Full-Range Transcendental Operations for SINE, COSINE, TANGENT, ARCTANGENT and LOGARITHM High Performance 80-Bit Internal Architecture