NECL Search Results

Contextual Info: MC100EP196B 3.3 V ECL Programmable Delay Chip With FTUNE Descriptions The MC100EP196B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar

Contextual Info: MC100EP195B 3.3V ECL Programmable Delay Chip Descriptions The MC100EP195B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and

N100

Abstract: NB100LVEP91 NB100LVEP91DW NB100LVEP91DWR2 qfn-24 4x4
Contextual Info: NB100LVEP91 2.5V / 3.3V Any Level Positive Input to −2.5V / −3.3V / −5V NECL Output Translator The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential

Contextual Info: MC10EP196, MC100EP196 Product Preview 3.3V/5VĄECL Programmable Delay Chip with FTUNE The MC10/100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It is identical to the

Contextual Info: NB100LVEP91 2.5V / 3.3V Any Level Positive Input to −2.5V / −3.3V / −5V NECL Output Translator http://onsemi.com Description The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential

HEP32

Abstract: MC10EP32DR2G 5P J TRANSISTOR MARKING
Contextual Info: MC10EP32, MC100EP32 3.3V / 5V ECL B2 Divider • 350 ps Typical Propagation Delay • Maximum Frequency > 4 GHz Typical Figure 3 • PECL Mode Operating Range: • VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V

Contextual Info: NB100LVEP91 2.5 V/3.3 V Any Level Positive Input to −2.5 V/−3.3 V/−5 V NECL Output Translator http://onsemi.com Description The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential

Contextual Info: MC10EP195, MC100EP195 3.3V / 5VĄECL Programmable Delay Chip The MC10/100EP195 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and

HEL33

Abstract: KEL33 EL33 MC100EL33 MC10EL33
Contextual Info: MC10EL33, MC100EL33 5V ECL ÷4 Divider Description Features • • Machine Model; > 100 V PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input Pulldown Resistors on CLK s and R.

VCF12

Abstract: LQFP-32 MC100 QFN32 QFN-32
Contextual Info: MC100EP196B 3.3 V ECL Programmable Delay Chip With FTUNE Descriptions The MC100EP196B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar

TQFP 100 socket

Contextual Info: MC10EP196, MC100EP196 Product Preview 3.3V/5VĄECL Programmable Delay Chip with FTUNE The MC10/100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It is identical to the

MC100EP195

Abstract: QFN-32 footprint MC10EP195 QFN32 7850 AE
Contextual Info: MC10EP195, MC100EP195 3.3V ECL Programmable Delay Chip The MC10/100EP195 is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. http://onsemi.com

K1648

Abstract: EL14 KEL1648 MC100EL1648 MC1648
Contextual Info: MC100EL1648 5 V ECL Voltage Controlled Oscillator Amplifier Description Features • • • • • • Typical Operating Frequency Up to 1100 MHz Low−Power 19 mA at 5.0 Vdc Power Supply PECL Mode Operating Range: VCC = 4.2 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V

MC100EP195

Abstract: MC100EP195FA MC100EP195FAR2 MC10EP195 MC10EP195FA MC10EP195FAR2
Contextual Info: MC10EP195, MC100EP195 3.3V / 5VĄECL Programmable Delay Chip The MC10/100EP195 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and

N100

Abstract: NB100LVEP91
Contextual Info: NB100LVEP91 2.5 V/3.3 V Any Level Positive Input to −2.5 V/−3.3 V NECL Output Translator http://onsemi.com Description The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential

HEL33

Abstract: MC10EL33 EL33 KEL33 MC100EL33 MC100EL33DG
Contextual Info: MC10EL33, MC100EL33 5V ECL ÷4 Divider Description Features • • Machine Model; > 100 V PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input Pulldown Resistors on CLK s and R.

kel16

Abstract: HEL16 E116 MC100EL16 MC10EL16
Contextual Info: MC10EL16, MC100EL16 5.0 V ECL Differential Receiver http://onsemi.com MARKING DIAGRAMS* 8 1 SOIC−8 D SUFFIX CASE 751 Features 190 ps Propagation Delay PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V

Contextual Info: NB100LVEP91 2.5 V/3.3 V Any Level Positive Input to -2.5 V/-3.3 V NECL Output Translator http://onsemi.com Description The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential

Contextual Info: MC100EP196A 3.3 V ECL Programmable Delay Chip With FTUNE The MC100EP196A is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further

Contextual Info: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar

MA E411

Abstract: AND8020 MC10E111 MC10E411 MC10E411FN MC10E411FNR2
Contextual Info: MC10E411 5VĄECL 1:9 Differential PECL/NECL RAMBus Clock Buffer The MC10E411 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The MC10E411’s function and performance are similar to the popular MC10E111, with the added feature of 1.2 V output swings.

432N

Abstract: DFC-1800 Trompeter CBBJR79 PRL-730 CBBJR79 Trompeter trompeter twinax PRL-433N waveform variable time delay with connector DIR100
Contextual Info: PRL-432N DUAL CH. UNIVERSAL DIFFERENTIAL 124 Ω INPUT TO COMPLEMENTARY 50 Ω NECL OUTPUT TRANSLATOR PRL-433N DUAL CH. DIFFERENTIAL 50 Ω NECL INPUT TO DIFFERENTIAL 124 Ω NECL OUTPUT TRANSLATOR APPLICATIONS • • • Essential Lab Tools for interfacing with High Speed

PRL-ACT-50

Abstract: PRL-460ANPD
Contextual Info: PRL-460ANPD DUAL CHANNEL NECL TO PECL TRANSLATOR PRL-460ANLPD DUAL CHANNEL NECL TO LVPECL TRANSLATOR APPLICATIONS o o o Converting Single Ended or Differential NECL Signals to Differential PECL or LVPECL Signals High Speed Digital Communications systems Testing

N100

Abstract: NB100LVEP91 NB100LVEP91DW NB100LVEP91DWR2 D 1875 d1875
Contextual Info: NB100LVEP91 Product Preview 2.5V / 3.3V Any Level Input to −2.5V / −3.3V / −5V NECL Output Translator The NB100LVEP91 is a triple any level input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential -2.5 V / -3.3