N208 Search Results

S-PBGA-N208

Contextual Info: MECHANICAL DATA MPBG042 – NOVEMBER 1997 GGW S-PBGA-N208 PLASTIC BALL GRID ARRAY 15,10 SQ 14,90 12,80 TYP 0,80 0,80 U T R P N M L K J H G F E D C B A 1 0,95 0,85 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1,40 MAX Seating Plane 0,12 0,08 0,55 0,45 0,08 M 0,45

Contextual Info: Date:- 02 August 2012 Data Sheet Issue:- 3 Phase Control Thyristor Types N2086NC060 to N2086NC100 Absolute Maximum Ratings VOLTAGE RATINGS MAXIMUM LIMITS UNITS VDRM Repetitive peak off-state voltage, note 1 600-1000 V VDSM Non-repetitive peak off-state voltage, (note 1)

Contextual Info: WESTCODE An Date:- 3 Jul, 2006 Data Sheet Issue:- 2 IXYS Company Provisional Data Wespack Phase Control Thyristor Types N2083QK080 to N2083QK140 Absolute Maximum Ratings VOLTAGE RATINGS MAXIMUM LIMITS UNITS VDRM Repetitive peak off-state voltage, note 1

Contextual Info: MECHANICAL DATA MPBG084 – NOVEMBER 1998 GLQ S-PLGA-N208 PLASTIC LAND GRID ARRAY 15,10 SQ 14,90 12,80 TYP 0,80 0,80 U T R P N M L K J H G F E D C B A 3 1 2 0,95 0,85 5 4 7 6 9 8 11 10 13 12 15 14 17 16 1,10 MAX Seating Plane 0,42 0,34 0,08 M 0,15 0,05 0,15

04.99

Contextual Info: MECHANICAL DATA MPBG104 – APRIL 1999 GFD S-PBGA-N208 PLASTIC BALL GRID ARRAY 23,20 SQ 22,80 20,20 SQ 19,00 20,32 TYP 1,27 1,27 U T R P N M L K J H G F E D C B A 1 3 2 5 4 7 6 9 8 11 10 13 12 15 14 17 16 2,32 MAX 1,17 NOM Seating Plane 0,40 0,30 0,90 0,60

2SB1203

Abstract: 2SD1803 2044B ITR09181 2SD1667
Contextual Info: 注文コード No. N 2 0 8 5 B 2SB1203/2SD1803 No. N2085B 41400 * 半導体ニューズ No.2085 ’ 87-88 データブック個別半導体素子トランジスタ編 No.2085A とさしかえてください。 2SB1203 / 2SD1803 PNP / NPN エピタキシァルプレーナ形シリコントランジスタ

N2086NS100

Abstract: N2086N N2086 N2086NS
Contextual Info: WESTCODE Date:- 6 Feb, 2001 Data Sheet Issue:- 1 Phase Control Thyristor Types N2086NS060 to N2086NS100 Absolute Maximum Ratings VOLTAGE RATINGS MAXIMUM LIMITS UNITS VDRM Repetitive peak off-state voltage, note 1 600-1000 V VDSM Non-repetitive peak off-state voltage, (note 1)

2SA1477

Abstract: N2089B 2SC3787 n2089
Contextual Info: 注文コード No.N 2 0 8 9 B 2SA1477 / 2SC3787 No. N2089B 20400 半導体ニューズ No.2089 ’ 91 大信号トランジスタ Vol.1 データブック No.2089A とさしかえてください。 2SA1477 / 2SC3787 用途 ・100W 電力増幅器のプリドライバ用。

N2083QK

Abstract: n2083qk140
Contextual Info: WESTCODE An Date:- 3 Jul, 2006 Data Sheet Issue:- 2 IXYS Company Provisional Data Wespack Phase Control Thyristor Types N2083QK080 to N2083QK140 Absolute Maximum Ratings VOLTAGE RATINGS MAXIMUM LIMITS UNITS VDRM Repetitive peak off-state voltage, note 1

N2086NS

Abstract: N2086NS100 N2086NS060-100 N610SH06-10 n610sh N2086NS060
Contextual Info: WESTCODE An Date:- 17 Mar, 2004 Data Sheet Issue:- 2 IXYS Company Phase Control Thyristor Types N2086NS060 to N2086NS100 Old Type No.: N610SH06-10 Absolute Maximum Ratings VOLTAGE RATINGS MAXIMUM LIMITS UNITS VDRM Repetitive peak off-state voltage, note 1

N370sH12

Abstract: N1114LS120-180 n540sh12 N370SH N280SH12-16 N390CH30-36 n200ch N195CH12-16 N280SH12 N195CH12
Contextual Info: Old Part Number PDF Data Sheet Available RECTIFIER DEVICE - Phase Control Thyristors - Capsule Types VDRM VRRM Range New Part Number IT AV @ Tsink o 55 C ITSM(1) ITSM(2) 10ms I2t(2) 10ms 10ms VR o VR ≤ 10V 25 C £10V ≤ 60% VRRM IT(RMS) @ Tsink VR di/dt Non

n20s

Abstract: A144 BG256 IEEE1164 Military Plastic pASIC 3 Family 256
Contextual Info: 3T PRELIMINARY CYPRESS Ultra38007 UltraLogic Very High Speed 7K Gate CMOS FPGA Features — Minimum Iol and Ioh 24 mA Flexible logic cell architecture — Wide fan-in up to 16 input gates — Multiple outputs in each cell — Very low cell propagation delay

2561b

Abstract: CPU 314 IFM 8kx1 RAM cy17 ALI chipset fast page mode dram controller CY2254ASC-2 CY27C010 CY82C691 CY82C693
Contextual Info: PRELIM INARY CY82C691 Pentium hyperCache™ Chipset System Controller Features Supports mixed standard page-mode and EDO DRAMs Supports the VESA Unified Memory Architecture VUMA Support for standard 72-bit-wide DRAM banks Supports non-symmetrical DRAM banks

1MD45

Abstract: cy17 High-Zt11-12 CY10 CY82C691 CY82C692 CY82C693 DQ23P cy82
Contextual Info: PRELIM INARY CY82C692 W CYPRESS Pentium hyperCache™ Chipset Data-Path Controller with Integrated Cache Features • Supports ail 3.3V Pentium™-class processors, AMD K5, K6 and Cyrix M1 CPUs • Two-bit wraparound counter supporting Intel Burst or Linear burst sequence

1de2

Abstract: northbridge circuit pentium 4 PS/2 KEYBOARD CONTROLLER 001H CY82C691 CY82C693UB intel 8042 keyboard controller 000B0000
Contextual Info: CY82C693UB P R E LIM IN A R Y hyperCache / Stand-Alone PCI Peripheral Controller with USB — CD ROM support Features PCI to ISA bridge PCI Bus Rev. 2.1 compliant Supports up to 5 additional PCI masters including the CY82C691 Integrated DMA controllers with Type A, B, and F sup­

CY37384

Abstract: CY37384V
Contextual Info: PRELIMINARY CY37384 UltraLogic 384-Macrocell ISR™ CPLD — tS = 5.5 ns Features • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • • • • • — Design changes don’t cause pinout changes

AAAG 6 pin ic

Abstract: n208
Contextual Info: CYPRESS Features PRELIMINARY UltraLogic Very High Speed 7K Gate CMOS FPGA — Minimum Iol and Ioh ° f 24 mA • Flexible logic cell architecture — Wide fan-in up to 16 input gates — Multiple outputs in each cell — Very low cell propagation delay

Contextual Info: • ■ J ^ m n r n n PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD — tco = 4.5 ns Features • 256 macrocells in sixteen logic blocks • In-System Reprogram mable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: ! ^ jjjjjy '•ttttttttWÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄW1- JM N K t t ♦ < ij / 5; PRELIMINARY *^ ' CY37384 UltraLogic 384-Macrocell ISR™ CPLD — ts = 5.5 ns Features — tco = 6 ns • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ (ISR™

Contextual Info: ^ jjjjjy .•/$ $$$$I ♦ PRELIMINARY < ij /t t5;*^ ' CY37512 UltraLogic 512-Macrocell ISR™ CPLD — tco = 6 ns Features • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ (ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

SFF-8038i

Contextual Info: CY82C693 CYPRESS_ Pentium hyperCache™ Chipset Peripheral Controller — CD ROM support Features • PCI to ISA bridge • PCI Bus Rev. 2.1 compliant • Supports up to 5 additional PCI masters including the CY82C691 • Integrated DMA controllers with Type A, B, and F sup­

Contextual Info: CYPRESS PRELIMINARY CY82C691 Pentium hyperCache™ Chipset System Controller Features Provides control for the cache, system memory, and the PCI bus PCI Bus Rev. 2.1 compliant Supports 3V Pentium™ , AMD K5, and Cyrix 6x86 M1 CPUs Support for WB or W T L1 cache

Contextual Info: Xgjf PRELIMINARY CY37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7 ns • 256 macrocells in sixteen logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.5 ns • • • • • • — JTAG-compliant on-board programming

Contextual Info: fax id: 6149 W CYPRESS Ultra37256V PRELIMINARY UltraLogic TM 256-Macrocell 3.3V ISR CPLD • Up to 192 1/Os — plus 5 dedicated inputs including 4 clock inputs Features • 256 macrocells in sixteen logic blocks • IEEE standard 3.3V operation — 3.3V ISR