MT4LC400 Search Results

Contextual Info: PRELIMINARY MT4LC4007J S 1 MEG X 4 DRAM DRAM 1 MEG x 4 DRAM 3.3V EDO PAGE MODE, OPTIONAL SELF REFRESH FEATURES • • • • • • • • • • Single +3.3V ±0.3V power supply Low power, 250|xW standby; lOOmW active, typical JEDEC-standard pinout and packages

Contextual Info: PRELIMINARY MT4LC4007J S 1 MEG X 4 DRAM I^IICRON 1 MEG x 4 DRAM DRAM FEATURES • • • • • • • • • • PIN ASSIGNMENT (Top View) Single +3.3V ±0.3V power supply Low power, 0.25mW standby; 115mW active, typical JEDEC-standard pinout and packages

MT4LC400

Contextual Info: MT4LC4001 J S 1 MEG X 4 DRAM M IC R O N DRAM 1 MEG x 4 DRAM 3.3V, FAST PAGE MODE OPTIONAL SELF REFRESH PIN ASSIGNMENT (Top View) • Single +3.3V ±0.3V power supply • Low power, 0.3m W standby; lOOmW active, typical • Industry-standard x4 pinout, tim ing, functions and

Contextual Info: ADVANCE MT4LC4001J S 1 MEG X 4 DRAM ICRGN 1 MEG X 4 DRAM DRAM 3.3V EXTENDED REFRESH SELF REFRESH FEATURES • Single +3.3V ±.3V power supply • Low power, 100|iW standby; 125mW active, typical • Industry-standard x4 pinout, timing, functions and packages

44c4001

Contextual Info: ADVANCE MICRON I MT4LC4001J S 1 RAM 1 MEG MEG X x 44 D DRAM SEMICSKUCTORMC DRAM 1 MEG x 4 DRAM 3.3V FAST-PAGE-MODE OPTIONAL SELF REFRESH FEATURES • Single+3.3V ±.3V power supply • Low power, 250^W standby; 150mW active, typical • Industry-standard x4 pinout, timing, functions and

Contextual Info: MT4LC4001 J S 1 MEG X 4 DRAM MICRON • TECHNO! OGY. INC 1 MEG x 4 DRAM DRAM 3.3V, FAST PAGE MODE OPTIONAL SELF REFRESH PIN A SSIG N M EN T (Top View) • Single +3.3V +0.3V power supply • Low power, 0.3mW standby; lOOmW active, typical • Industry-standard x4 pinout, timing, functions and

Contextual Info: MT4LC4001 J S 1 MEG X 4 DRAM l^ iic n o N 1 MEG x 4 DRAM DRAM FEATURES • Single +3.3V + .3V pow er supply • Low power, 250nW standby; lOOmW active, typical • Industry-standard x4 pinout, timing, functions and packages • High-performance CMOS silicon-gate process

Contextual Info: PRELIMINARY V lIC R O r V ! 1 MT4LC4007J(S MEG X 4 DRAM 1 MEG x 4 DRAM DRAM FEATURES • • • • • • • • • • Single +3.3V ±0.3V power supply Low power, 0.25m W standby; 115mW active, typical JEDEC-standard pinout and packages High-perform ance CM OS silicon-gate process

A817B

Abstract: SOT23-5 marking MAV operational
Contextual Info: ADVANCE MT4LC4001J S 1 MEG x 4 DRAM I^ IIC R O N DRAM 1 MEG x 4 DRAM 3.3V EXTENDED REFRESH SELF REFRESH FEATURES • Single +3.3V ±.3V power supply • Low power, 100|iW standby; 125mW active, typical • Industry-standard x4 pinout, tim ing, functions and

WT16LD

Abstract: tc 97101 INTERNAL DIAGRAM OF IC 7476
Contextual Info: PRELIMINARY M IC n a iM 1 M T 16LD T 164(S), M T16LD(T)464(X)(S) 1 MEG, 4 MEG X 64 DRAM M OD ULES 1 MEG, 4 MEG x 64 DRAM MODULE 8, 32 MEGABYTE, 3.3V, OPTIONAL SELF REFRESH, FAST PAGE OR EDO PAGE MODE FEATURES • JEDEC- and industry-standard pinout in a 168-pin,

precon ten

Contextual Info: PRELIMINARY 1 MEG x 4 DRAM DRAM 3.3V EDO PAGE MODE, OPTIONAL SELF REFRESH FEATURES • • • • • • • • • • PIN ASSIGNMENT Top View Single +3.3V ±0.3V power supply Low power, 250|iW standby; lOOmW active, typical JEDEC-standard pinout and packages

tc 97101

Contextual Info: ADVANCE |V |C = R O N 1 MEG DRAM MODULE X MT16LD T 164(S) 64 DRAM MODULE 1 MEG x 64 DRAM FEATURES • Industry-standard pinout in a 168-pin, dual read-out, single-in-line package • High-perform ance CM OS silicon-gate process • Single +3.3V +0.3V power supply

Contextual Info: ADVANCE M IC m n N 1 MT8LD T 132(X)(S), M T16LD(T)232(X)(S) 1 MEG, 2 MEG X 32 DRAM M ODULES DRAM 1 m e g , 2 MEG x 32 4, 8 MEGABYTE, 3.3V, OPTIONAL SELF M O D U L E m o d e ESH’ FAST PAGE ° R ED° PAGE FEATURES PIN ASSIGNMENT (Front View) OPTIONS Timing

4c4001jd

Abstract: D-22A mt4m0
Contextual Info: M I I C R O N D 22A 4 M E G D R A M D IE T DRAM DIE 4 MEG DRAM 1 MEG X 4, 4 M E G x 1 FEATURES • • • • Single 5.0V or 3.3V power supply Industry-standard timing and functions High-performance CMOS silicon-gate process All inputs, outputs and clocks are TTL- and CMOScompatible

D-22A

Contextual Info: MI CR ON S E M I C O N D U C T O R INC b^E ]> • b l l l S M T D G 1 D D 1 E 2ÖD ■ fIRN MICRON I D 22A 4 MEG DRAM DIE SEMICONDUCTOR IKC DRAM DIE 4 MEG DRAM 1 MEG X 4, 4 MEG x 1 FEATURES • • • • Single 5.0V or 3.3V power supply Industry-standard timing and functions

Contextual Info: M T4LC 4001J S 1M EGX 4 D R A M MICRON I 1 1 MEG x 4 DRAM DRAM FEATURES • Single +3.3V ±.3V power supply • Low power, 250|xW standby; 100m W active, typical • Industry-standard x4 pinout, timing, functions and packages • High-performance CMOS silicon-gate process

Contextual Info: H C R O N SEM ICONDUCTOR INC b7E D • blllS4'i ODOTÖMT T47 ■ URN PRELIMINARY M T4LC 4007J S " JM E Gx4 D R A M MICRON I s e » .c o m > u !:to i« c DRAM 1 MEG x 4 DRAM 3.3V EDO PAGE MODE, OPTIONAL SELF REFRESH FEATURES • • • • • • • •

Contextual Info: PRELIMINARY MT8LD132 S , MT16LD232(S) 1 MEG, 2 MEG x 32 ORAM MODULE MICRON H SEMICONDUCTOR INC. 1 MEG, 2 MEG x 32 4, 8 MEGABYTE, 3.3V, FAST PAGE MODE, OPTIONAL SELF REFRESH FEATURES • In d u stry -stan d ard p in o u t in a 72-pin single-in-line package

Contextual Info: PRELIMINARY M IC Z R C D ÍS i 1 M T18LD T 172(S ), M T18LD (T )472(X )(S ) 1 MEG. 4 MEG x 72 DRAM M O D U LE S DRAM 1 MEG, 4 MEG x 72 _ _ _ _ _ _ _ _ M n n t II F IV IV U U I.L 8, 32 MEGABYTE, ECC, 3.3V, OPTIONAL SELF REFRESH, FAST PAGE OR EDO PAGE MODE

Contextual Info: PRELIMINARY M M Q N MT16LD T 164(S), MT16LD(T)464(X)(S) 1 MEG, 4 MEG X 64 DRAM MODULES I DRAM |y | 0 Q 18, 32MEG’ 4 MEG x 64 MEGABYTE, 3.3V, OPTIONAL SELF L £ REFF^ESH, FAST PAGE OR EDO PAGE FEATURES PIN ASSIGNMENT (Front View) 168-Pin DIMM • JEDEC- and industry-standard pinout in a 168-pin,

Contextual Info: DRAM DIE 4 MEG DRAM 1 MEG X 4, 4 MEG x 1 FEATURES Single 5.0V or 3.3V pow er supply Industry-standard timing and functions High-performance CMOS silicon-gate process All inputs, outputs and clocks are TTL- and CMOScompatible • Refresh modes: RAS ONLY, CAS-BEFORE-RAS CBR ,

Contextual Info: ADVANCE MT8LD132 X S , MT16LD232X(S) 1 MEG, Z MEG X 32 DRAM MODULE 1 MEG, 2 MEG x 32 DRAM MODULE 4, 8 MEGABYTE, 3.3V, EDO PAGE MODE, OPTIONAL SELF REFRESH FEATURES • New proposed JED EC-standard pinout in a 72-pin single-in-line package • High-performance CM O S silicon-gate process

001245b

Abstract: 16 MB Micron EDO SIMM Module PC25N
Contextual Info: ADVANCE M IC R O N MT8LD T 132(X)(S), MT16LD(T)232(X)(S) -I MEG, 2 MEG X 32 DRAM MODULES • □ R Iv i O A M D U 1 m e g , 2 M E G x 3 2 4, 8 MEGABYTE, 3.3V, OPTIONAL SELF L E modeesh ’ fa st pa g e o r ed o pa g e FEATURES • JEDEC-standard pinout in a 72-pin single-in-line