MIPS V CACHE Search Results

Contextual Info: Preliminary Data Sheet July 1995 m A T& T Microelectronics DSP1605 Digital Signal Processor 1 Features 2 Description • For 5 V operation: — 25 ns instruction cycle time 40 MIPS — 30 ns instruction cycle time (33 MIPS) ■ For 3.3 V operation: — 31.25 ns instruction cycle time (32 MIPS)

lt228

Abstract: b433 resonator CD 4017 PIN DIAGRAM SDL 4007 TT 2146 4043-C DB3C 828 F3L3 AB14C wy 413
Contextual Info: Preliminary Data Sheet i uy ü AT&T Microelectronics DSP1604/06 Digital Signal Processor •I 1 Features 2 Description ■ For 5 V operation: — 25 ns instruction cycle time 40 MIPS — 30 ns instruction cycle time (33 MIPS) ■ For 3.3 V operation: — 31.25 ns instruction cycle time (32 MIPS)

jalr

Abstract: UPD30111 DSRL32 mips16 instruction set
Contextual Info: ¿¿PD30111 NEC 22. INSTRUCTION SET The V r4111 has two types of instructions: 32-bit instructions MIPS III and 16-bit instructions (MIPS16). 22.1 MIPS III Instruction Each instruction of the MIPS III consists of 1 word (32 bits) located at a word boundary. Three instruction formats

intel 4040

Abstract: DSP1605 5-4001 DB3C intel 4008 te 4017 tl 4013 540T2 motorola XT 1606 RM RSTB14
Contextual Info: Preliminary Data Sheet July 1995 £ 3 A TgT Microelectronics DSP1605 Digital Signal Processor • 1 Features 2 Description ■ For 5 V operation: — 25 ns instruction cycle time 40 MIPS — 30 ns instruction cycle time (33 MIPS) ■ For 3.3 V operation:

44-PIN

Abstract: 68HC11 DSP1609 DSP1609F HC11 DSP1600 lucent 451
Contextual Info: Preliminary Data Sheet July 1999 FlashDSP 1609F Digital Signal Processor 1 Features • ■ 12.5 ns instruction cycle time 80 MIPS at 3.3 V operation Power-saving features: — Low-power 0.35 µm CMOS technology; fully static design — Active power: 6.5 mW/MIPS at 3.3 V

MIPS16

Abstract: System on a chip VR4102
Contextual Info: m ec NEC Electronics Inc. VR4111 jiPD30111 64-Bit MIPS RISC Microprocessor Product Brief September 1997 Description The 64-bit V r41 11 (nPD30111 ) microprocessor is a member of NEC’s V r Series™ devices created for Windows CE-based embedded consumer applications. Designed around the popular MIPS®

CSP1009

Abstract: 1600-HDS 310F4
Contextual Info: Advance Data Sheet July 1999 B900 Baseband Signal Processor 1 Features 2 Description • For 5 V operation: — 12.5 ns instruction cycle time 80 MIPS (See Table 89 on page 71.) ■ For 3.3 V operation: — 16.7 ns instruction cycle time (60 MIPS) (See Table 89 on page 71.)

1741 OPamp

Abstract: t152 act dsp1653 mip 0244 lucent 451
Contextual Info: Preliminary Data Sheet January 1998 FlashDSP 1650 Digital Signal Processor 1 Features • For 5 V operation: — 25 ns instruction cycle time 40 MIPS ■ For 3.3 V operation: — 30 ns instruction cycle time (33 MIPS) ■ Power-saving features: — Low-power 0.6 µm CMOS technology; fully

Contextual Info: Introduction The V r 4100 microprocessor is a low-cost, low-power microprocessor that is compatible with the M IPS I, MIPS II, and MIPS III Instruction Set Architecture ISA , except for the Floating-point operating instructions, LL/LLD instruction and SC/SCD instruction.

Contextual Info: Preliminary Data Sheet January 1998 m i c r o e l e c t r o n i c s group Lucent Technologies Bell Labs Innovations FlashDSP 1650 Digital Signal Processor 1 Features For 5 V operation: — 25 ns instruction cycle time 40 MIPS For 3.3 V operation: — 30 ns instruction cycle time (33 MIPS)

Contextual Info: ^ AT&T Preliminary Data Sheet July 1995 Microelectronics DSP1604/06 Digital Signal Processor 1 Features 2 Description • For 5 V operation: — 25 ns instruction cycle time 40 MIPS — 30 ns instruction cycle time (33 MIPS) The DSP1604/06 is a 16-bit fixed-point digital signal

Contextual Info: a PRELIMINARY Am29040 Advanced Micro Devices High-Performance RISC Microprocessor with Instruction and Data Caches DISTINCTIVE CHARACTERISTICS • Full 32-bit architecture ■ 3.3-V operation with 5-V-tolerant I/O ■ 66.8 VAX MIPS sustained at 50 MHz ■

Am29050 Microprocessor Users Manual

Abstract: AM29035 AM29040 Am29000 Users Manual 18458 CGM145 PDR144 602-7639 MiniMON29K Am29050TM
Contextual Info: PRELIMINARY Am29040 Advanced Micro Devices High-Performance RISC Microprocessor with Instruction and Data Caches DISTINCTIVE CHARACTERISTICS Full 32-bit architecture 3.3-V operation with 5-V-tolerant I/O 66.8 VAX MIPS sustained at 50 MHz Low-power Snooze and Sleep modes

Contextual Info: TMS320C31, TMS320LC31 DIGITAL SIGNAL PROCESSORS SPRS035B - MARCH 1996 - REVISED JANUARY 1999 High-Performance Floating-Point Digital Signal Processor DSP : - TMS320C31-80 (5 V) 25-ns Instruction Cycle Time 440 MOPS, 80 MFLOPS, 40 MIPS - TMS320C31-60 (5 V)

P1020

Abstract: PI019
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT _ ¿¿PD30111 V r4111 64-/32-BIT MICROPROCESSOR DESCRIPTION The /xPD30111 V r4111 is one of NEC's V r Series RISC (Reduced Instruction Set Computer) microprocessors and is a high-performance 64-/32-bit microprocessor employing the MIPS

120-pin

Abstract: 120-pin, microprocessor r4305 NEC r4305
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT UPD30200, 30210 V r4300 , V r4305™, V r4310™ 64-BIT MICROPROCESSOR The /XPD30200 V r4300 , 30200-133 (V r4305), and 30210 (VR4310)Note are high-performance, 64-bit RISC (Reduced Instruction Set Computer) type microprocessors employing the RISC architecture developed by MIPS.

21JT

Abstract: c3040
Contextual Info: TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A - APRIL 1996 - REVISED JUNE 1997 High-Performance Floating-Point Digital Signal Processor DSP - TMS320C30-50 (5 V) 40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS - TMS320C30-40 (5 V) 50-ns Instruction Cycle Time

mb86901

Contextual Info: F U J IT S U High Performance 32-Bit RISC Processor SPARC FEATURES • Architecture supports scalability towards faster technologies • Address presentation which supports highperformance cache • 15 times V A X ™ 11/780 equivalent MIPS typical performance

Contextual Info: TMS320C31, TMS320LC31 DIGITAL SIGNAL PROCESSORS SPRS035B - MARCH 1996 - REVISED JANUARY 1999 D High-Performance Floating-Point Digital D D D D D Signal Processor DSP : - TMS320C31-80 (5 V) 25-ns Instruction Cycle Time 440 MOPS, 80 MFLOPS, 40 MIPS - TMS320C31-60 (5 V)

Contextual Info: TMS320C31, TMS320LC31 DIGITAL SIGNAL PROCESSORS SPRS035B - MARCH 1996 - REVISED JANUARY 1999 D High-Performance Floating-Point Digital D D D D D Signal Processor DSP : - TMS320C31-80 (5 V) 25-ns Instruction Cycle Time 440 MOPS, 80 MFLOPS, 40 MIPS - TMS320C31-60 (5 V)

p5A MARKING

Contextual Info: TMS320C31, TMS320LC31 DIGITAL SIGNAL PROCESSORS SPRS035B - MARCH 1996 - REVISED JANUARY 1999 D High-Performance Floating-Point Digital D D D D D Signal Processor DSP : - TMS320C31-80 (5 V) 25-ns Instruction Cycle Time 440 MOPS, 80 MFLOPS, 40 MIPS - TMS320C31-60 (5 V)

NEC 32bit Processor

Contextual Info: VR 4310 64-Bit MIPS RISC Microprocessor for Windows CE Product Brief Description February 1998 The 64-bit V r431 0 pPD30210 RISC microprocessor is one of NEC’s V r Series™ families supporting Windows CE-based embedded consumer applications. Designed

Contextual Info: TMS320C31, TMS320LC31 DIGITAL SIGNAL PROCESSORS SPRS035B - MARCH 1996 - REVISED JANUARY 1999 D High-Performance Floating-Point Digital D D D D D Signal Processor DSP : - TMS320C31-80 (5 V) 25-ns Instruction Cycle Time 440 MOPS, 80 MFLOPS, 40 MIPS - TMS320C31-60 (5 V)

Contextual Info: TMS320C31, TMS320LC31 DIGITAL SIGNAL PROCESSORS SPRS035B - MARCH 1996 - REVISED JANUARY 1999 D High-Performance Floating-Point Digital D D D D D Signal Processor DSP : - TMS320C31-80 (5 V) 25-ns Instruction Cycle Time 440 MOPS, 80 MFLOPS, 40 MIPS - TMS320C31-60 (5 V)