METAL 3055 TRANSISTOR Search Results

8 pin ic 3773

Contextual Info: METAL-CAN TRANSISTORS CONTINENTAL DEVICE INDIA 35E D • E3B33cm 000DQ5M =1 ■ 33-/3 PROFESSIONAL/COMMERCIAL GRADE APPLICATION GENERAL PURPOSE POWER TRANSISTORS IN TO-2Q4AA PACKAGE Polarity Ic VCE0 SUS hFE@ Ic & VCE min/max Device 2N 3055 2N 3232 2N 3442

marking 3055

Abstract: 3055F
Contextual Info: FEATURES LT3055 500mA, Linear Regulator with Precision Current Limit and Diagnostics DESCRIPTION n n n n n n The LT 3055 is a micropower, low noise, low dropout voltage LDO linear regulator. The device supplies 500mA of output current with a dropout voltage of 350mV. A 10nF

BDX 241

Abstract: BD 35 transistor 3055 transistor TRANSISTOR BDX transistor 3055 transistor BUx 49 transistor BD 140 TRANSISTOR BDX 14 transistor 2N 3055 transistor bd 905
Contextual Info: TOP-3 general purpose transistor selector guide y guide de sélection transistors TO P-3 usage général THOMSON-CSF ^ \ \ C E O (sus 45V 60V 80V 100V BD 249 BD 249A BD 249B BD 249C BD 250 BD 250A BD 250B BD 250C Case 25 A T0-220AB general purpose transistor selector guide

Contextual Info: FEATURES LT3055 Series 500mA, Linear Regulator with Precision Current Limit and Diagnostics DESCRIPTION n n n n n n The LT 3055 series are micropower, low noise, low dropout voltage LDO linear regulators. The devices supply 500mA of output current with a dropout voltage of 350mV. A 10nF

class d amplifier schematic hip4080

Abstract: HIP4080 amplifier circuit diagram class D AN9404 AN9539 mosfet L 3055 1350P AN9405 0-60V HIP2060 MO-169AB
Contextual Info: TM No. AN9539 Intersil Intelligent Power May 1996 HIP2060, N-Channel Half-Bridge Power MOSFET Array Author: Edwin C. Jabillo Abstract The HIP2060 is a dual MOSFET array topology in a half-bridge configuration which represents a new innovation of power semiconductor devices that integrates two matched power transistors in a chip. The HIP2060 power MOSFET array is an

class d amplifier schematic hip4080

Abstract: hip4080 h-bridge gate drive schematics circuit HIP4080 amplifier circuit diagram class D oscilloscope schematic EAS 200 lem la 50p mosfet p 3055 RM1S HIP2060 mosfet L 3055 high power fet audio amplifier schematic
Contextual Info: Harris Semiconductor No. AN9539 Harris Intelligent Power May 1996 HIP2060, N-Channel Half-Bridge Power MOSFET Array Author: Edwin C. Jabillo Abstract The HIP2060 is a dual MOSFET array topology in a half-bridge configuration which represents a new innovation of power semiconductor devices that integrates two matched power transistors in a chip. The HIP2060 power MOSFET array is an

HIP4080 amplifier circuit diagram class D

Abstract: class d amplifier schematic hip4080 jfet normally off to220 mosfet L 3055 HIP4080 ITL5-1 dual jfet transistor array AN9404 oscilloscope schematic EAS 200 Switching Power supply with HIP4080A
Contextual Info: No. AN9539 Intersil Intelligent Power May 1996 HIP2060, N-Channel Half-Bridge Power MOSFET Array Author: Edwin C. Jabillo Abstract The HIP2060 is a dual MOSFET array topology in a half-bridge configuration which represents a new innovation of power semiconductor devices that integrates two matched power transistors in a chip. The HIP2060 power MOSFET array is an

E131

Abstract: MC100EP131 MC10EP131 QFN32
Contextual Info: MC10EP131, MC100EP131 3.3V / 5V ECL Quad D Flip−Flop with Set, Reset, and Differential Clock Description The MC10/100EP131 is a Quad Master−slaved D flip−flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables.

mj2955

Contextual Info: 2N3055 MJ2955 COMPLEMENTARY SILICON POWER TRANSISTORS • STMicroelectronics PREFERRED SALESTYPES . COMPLEMENTARY NPN-PNP DEVICES DESCRIPTION The 2N3055 is a silicon Epitaxial-Base Planar NPN transistor mounted in Jedec TO-3 metal case. It is intended for power switching circuits, series

MARKING CODE D3B

Contextual Info: MC10EP101, MC100EP101 3.3V / 5VĄECL Quad 4-Input OR/NOR The MC10/100EP101 is a Quad 4–input OR/NOR gate. The device is functionally equivalent to the E101. With AC performance faster than the E101 device, the EP101 is ideal for applications requiring the

LQFP-32

Abstract: MC100EP101 MC100EP101FA MC100EP101FAR2 MC10EP101 MC10EP101FA MC10EP101FAR2 MARKING CODE D3B
Contextual Info: MC10EP101, MC100EP101 3.3V / 5V ECL Quad 4−Input OR/NOR The MC10/100EP101 is a Quad 4-input OR/NOR gate. The device is functionally equivalent to the E101. With AC performance faster than the E101 device, the EP101 is ideal for applications requiring the

MC100EP101

Abstract: MC100EP101FA MC100EP101FAR2 MC10EP101 MC10EP101FA MC10EP101FAR2
Contextual Info: MC10EP101, MC100EP101 3.3V / 5VĄECL Quad 4-Input OR/NOR The MC10/100EP101 is a Quad 4–input OR/NOR gate. The device is functionally equivalent to the E101. With AC performance faster than the E101 device, the EP101 is ideal for applications requiring the

MC100EP142

Abstract: MC10EP142 QFN32 JEDEC qfn tray
Contextual Info: MC10EP142, MC100EP142 3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in

Contextual Info: MC10EP101, MC100EP101 3.3V / 5VĄECL Quad 4-Input OR/NOR The MC10/100EP101 is a Quad 4–input OR/NOR gate. The device is functionally equivalent to the E101. With AC performance faster than the E101 device, the EP101 is ideal for applications requiring the

100EP131

Abstract: 87-3A E131 MC100EP131 MC100EP131FA MC100EP131FAR2 MC10EP131 MC10EP131FA MC10EP131FAR2
Contextual Info: MC10EP131, MC100EP131 3.3V / 5VĄECL Quad D Flip-Flop with Set, Reset, and Differential Clock The MC10/100EP131 is a Quad Master–slaved D flip–flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables.

100ep451

Abstract: MC100EP451 MC100EP451FA MC100EP451FAR2 MC10EP451 MC10EP451FA MC10EP451FAR2
Contextual Info: MC10EP451, MC100EP451 3.3V / 5VĄECL 6-Bit Differential Register with Master Reset The MC10/100EP451 is a 6–bit fully differential register with common clock and single ended Master Reset MR . It is ideal for very high frequency applications where a registered data path is necessary.

TQFP-32 socket

Contextual Info: MC10EP451, MC100EP451 3.3V / 5VĄECL 6-Bit Differential Register with Master Reset The MC10/100EP451 is a 6–bit fully differential register with common clock and single ended Master Reset MR . It is ideal for very high frequency applications where a registered data path is necessary.

Contextual Info: MC10EP131, MC100EP131 3.3V / 5VĄECL Quad D Flip-Flop with Set, Reset, and Differential Clock The MC10/100EP131 is a Quad Master–slaved D flip–flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables.

tqfp 64 thermal resistance

Abstract: marking CODE D2B
Contextual Info: MC10EP105, MC100EP105 3.3V / 5VĄECL Quad 2-Input Differential AND/NAND The MC10/100EP105 is a quad 2–input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device,

MC100EP451

Abstract: MC100EP451FA MC100EP451FAR2 MC10EP451 MC10EP451FA MC10EP451FAR2
Contextual Info: MC10EP451, MC100EP451 3.3V / 5VĄECL 6-Bit Differential Register with Master Reset The MC10/100EP451 is a 6–bit fully differential register with common clock and single ended Master Reset MR . It is ideal for very high frequency applications where a registered data path is necessary.

Contextual Info: MC10EP101, MC100EP101 3.3V / 5V ECL Quad 4−Input OR/NOR Description The MC10/100EP101 is a Quad 4−input OR/NOR gate. The device is functionally equivalent to the E101. With AC performance faster than the E101 device, the EP101 is ideal for applications requiring the

EP105

Abstract: MC100EP105 MC100EP105FA MC100EP105FAR2 MC10EP105 MC10EP105FA MC10EP105FAR2
Contextual Info: MC10EP105, MC100EP105 3.3V / 5VĄECL Quad 2-Input Differential AND/NAND The MC10/100EP105 is a quad 2–input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device,

MC100EP451

Abstract: MC100EP4511FA MC100EP451FAR2 MC10EP451 MC10EP451FA MC10EP451FAR2
Contextual Info: MC10EP451, MC100EP451 Product Preview 3.3V / 5VĄECL 6-Bit Differential Register with Master Reset The EP451 is a 6–bit fully differential register with common clock and single ended Master Reset MR . It is ideal for very high frequency applications where a registered data path is necessary.

100ep451

Abstract: MC100EP451 MC100EP451FA MC100EP451FAR2 MC10EP451 MC10EP451FA MC10EP451FAR2
Contextual Info: MC10EP451, MC100EP451 3.3V / 5VĄECL 6-Bit Differential Register with Master Reset The MC10/100EP451 is a 6–bit fully differential register with common clock and Single–Ended Master Reset MR . It is ideal for very high frequency applications where a registered data path is