MEMOR Search Results

UM5583

Abstract: UM55 SPKP rs 355 integrated circuits 5583H
Contextual Info: UMC UM5583 3 Sec Recording / Playback 1C Features • "BEEP" sound indicates to start recording and memory full for manual playback ■ Built-In AGC Automatic Gain Control to enlarge input dynamic range ■ Built-in low pass filter ■ Built-in microphone amplifier

TC9303AN

Abstract: 6LW6 TC9303 tc9304f LCD12 TC9319F TC9301AN TC9309F
Contextual Info: Digital Tuning System DTS (1) System IC-LSI System No. Controller PLL prescaler DTS-9 A3 Operating Voltage Crystal Oscittation TC9301AN TC9172AP 4.5-5.5V 7.2MHz TC9303AN TC9227P 4.5-5.5V 7.2MHz Major Functions Receiving Band Preset Memory * Station Clock

IR 30 D1

Contextual Info: SN74ALS236 64 x 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS107A-OCTOBER 1986 - REVISED SEPTEMBER 1993 Asynchronous Operation Organized as 64 Words by 4 Bits DW OR N PACKAGE TOP VIEW r NC [ 1 Data Rates From 0 to 30 MHz 3-State Outputs 16 J VCC 15 ] S O

tr8c

Abstract: TMS28F200
Contextual Info: TMS28F20ÛBZT, TMS28F200BZB 262144 BY 8-BIT/131072 BY 16-BIT BOOT-BLOCK FLASH MEMORIES SWS2dOO - JUNE 1 9 9 4 - REVISED SEPTEMBER 1997 • ■ I I I • • • • • • • • • • Organization . . . 262144 by 8 bits 131072 by 16 bits Array-Blocking Architecture

SMNS405A

Abstract: cms405 CMS408 CMS406
Contextual Info: CMS405, CMS406 4 MEGABYTE CMS407, CMS408 2 MEGABYTE DRAM MEMORY CARDS SMNS405A-JUNE1991-REVISED JANUARY 1993 * Credit Card Size 85.6 mm x 54 mm x 60-PIN MEMORY CARD (CONNECTOR VIEW 3.4 mm) Single 5-V Power Supply (±5% Tolerance) * Enhanced Page Mode Operation

UZ210

Abstract: P1275
Contextual Info: TOSHIBA MOS MEMORY PRODUCTS TMM27512ADI-20, TMM27512ADI-25 DESCRIPTION The TMM27512ADI is a 65,536 words * 8 bits ultraviolet light erasable and electri­ cally programmable read only memory. For read operation, the TMM27512ADI's access time is 200ns/250ns, and the TMM27512ADI

Contextual Info: TMS28C64 65,536-BIT ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY • Organization 8K x 8 • Single 5-V Power Supply ± 10% N AND J PACKAGES (TOP VIEW } Q 1 U A 12C 2 A7C 3 Compatible with Existing 64K M O S EPRO M s. PRO M s. R O M s, and EEPR O M s

Contextual Info: TC55417P/J —15H. TC55417P/J-20H TC55417P/J—25H. TC55417P/J-35H • * 16,384 W O R D x 4 BIT CMOS STATIC RAM DESCRIPTION The TC55417P/J—H is a 65,536 bit high speed static random access memory organized as 16,384 words by 4 bits using CMOS technology, and operated from a single 5 - volt supply.

TMS4116

Abstract: TMS4132
Contextual Info: MOS LSI TMS 4132 JDL 32,768-BIT DYNAMIC RANDOM-ACCESS MEMORY NOVEMBER 1979 32,768 «AX SUPPLY 1 X 1 Organization 10% Tolerance on All Supplies • All Inputs Including Clocks TTL-Compatible

Contextual Info: SN74ALS233B 16x5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SCAS253 - MARCH 1990 - REVISED JUNE 1992 • Independent Asychronous Inputs and Outputs DW OR N PACKAGE TOP VIEW • 16 Words by 5 Bits OE [ 1 FULL-1 [ 2 • Data Rates From 0 to 40 MHz • Fall-Through Ti me. . . 14 ns Typ

74ALS234

Contextual Info: SN54ALS234, SN74ALS234 64 x 4 ASYNCHRONOUS FIRST-IN FIRST OUT MEMORY 0 2 9 5 8 , OCTOBER 1 9 8 6 Asynchronous Operation S N 54A LS 234 . . . J PACKAGE S N 74A LS 234 . . . 0 OR N PACKAGE Organized as 6 4 Words of 4 Bits Management Products TOP VIEW! Data Rates from 0 to 30 MHz

tms4256

Abstract: TMS4266
Contextual Info: INSTR TM4256EL9, TM4256GU9 262,144 BY 9-BIT DYNAMIC BAM MODULES 7“-ifc-23-/7 25E D SEPTEMBER 1986 — REVISED M ARCH 1968 A SIC /MEMORY 262,144 x 9 Organization TM4266EL9 . . . L SMQLE-IN-UNE PACKAGE (TOP VIEWl_ Slngla 5-V Supply (10% Tolerance)

54256AP

Abstract: TC54256AF 54256a TC54256P 54256AF tmm23256p 27256D tc54256ap
Contextual Info: TOSHIBA TC54256AP/AF SILICON STACKED GATE CMOS 32,768 WORD x 8 BIT ONE TIME PROGRAMMABLE READ ONLY MEMORY D e s c rip tio n The TC54256AP/AF is a 32,768 word x 8 bit one time programm able read only m em or/ m olded in a 28-pin plastic package. The TC54256AP/AF’s access time is 200ns and it has a low power standby m ode which reduces the power dissipation without

Contextual Info: SN74ALS2541 OCTAL UNE DRIVERS/MOS DRIVERS WITH 3-STATE OUTPUTS JU NE 1984 - REV ISED M A Y 19M 3-Stata Outputs Drive Bus Lina« or Buffar Memory Address Registers • S N 7 4 A L S 2 S 4 1 . . D W O H N P A C K A G E T O P V IE W P-N-P Inputs Reduce D-C Loading

A1051

Contextual Info: TMS27C291, TMS27C292 16.384-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORIES TMS27PC291 16,384-BIT PROGRAMMABLE READ-ONLY MEMORY SEPTEM BER 1986 —REVISED APRIL 1988 Organization . . . 2K x 8 J AND N PA C KA G E Pin Compatible with Existing 2K x 8 Bipolar/High-Speed CM OS EPROMs

Contextual Info: S N 5 4 A LS 2 2 9 A , S N 7 4 A LS 2 2 9 A 1 6 x 5 ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORIES D 2 8 7 6 . M A R C H 1 9 8 6 -R E V IS E D M A Y 1 9 8 6 • Independent Asychronous Inputs and Outputs • 16 Words by 5 Bits Each • Data Rates from 0 to 30 MHz

27C020-12

Abstract: 27PC020-12 LS020 A1025 LS020B 2097152-BIT
Contextual Info: TMS27C020 2097152-BIT UV ERASABLE PROGRAMMABLE TMS27PC020 2097152-BIT PROGRAMMABLE READ-ONLY MEMORY SM LS020B - N O V E M B E R 1990 - REVISED JU N E 1995 • Organization . . . 256K x 8 J PACKAGE TOP VIEW • Single 5-V Power Supply • Operationally Compatible With Existing

260-pin

Contextual Info: TOSHIBA TC55V1864J/FT-10/12/15 PRELIMINARY SILICON GATE CMOS 65,536 WORD x 18 BIT CMOS STATIC RAM Description TheTC55V1864J/FT is a 1,179,648 bit high speed CMOS static random access memory organized as 65,536 words by 18 bits and operated from a single 3.3V : upply. Toshiba’s advanced CMOS technology and circuit design enable high speed operation.

Contextual Info: TOSHIBA TC58V64FT/DC TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 64-MBIT 8M X 8 BITS CMOS NAND E2PROM DESCRIPTION The TC58V64FT/DC is a single 3.3-V 64-Mbit (69,206,016-bit) NAND electrically erasable and programmable read-only memory (NAND E2PROM) organized as 528 bytes X 16 pages X 1024 blocks.

Contextual Info: UT54ACS541/UT54ACTS541 Radiation-Hardened Octal Buffers & Line Drivers, Three-State Outputs FEATURES • Three-state outputs drive bus lines or buffer memory address registers • l.2\i radiation-hardened CMOS - Latchup immune • High speed • Low power consumption

74F138

Contextual Info: S N 5 4 F13 8 , S N 74 F13 8 3-LINE TO 8-LINE D EC O D ERS/D EM U LTIPLEXERS D2932, MARCH 1987 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems S N 54F138 . . . J PACKAGE SN 74F138 . . . D OR N PACKAGE TOP VIEW AC 1 U ,6 3 vcc

Contextual Info: SILICON STACKED GATE MOS INTEGRATED CIRCUIT - TC57256AD-12,-120,-150 32 , 768 W O R D x 8 B I T C M O S UV ERASABLE A N D ELECTRICALLY PROGRAMMABLE READ ONLY MEMORY IDESCRIPTIONI The TC57256AD is a 32,768 word x 8 bit CMOS ultraviolet light erasable and electri­

Contextual Info: • ■ ! ■ ■ ■ ■ • '|<f TOSHIBA MIOS MEMORY PRODUCTS 8,192 WORD X 8 BIT CM OS STATIC RAM SILICON GATE C M O S T C 5 5 63 A P L-1 0, T C 5563A P L-12 T C 55 6 3 A P L -1 5 DESCRIPTIO N The TC5563APL is 65,536 bit static random access memory organized as 8,1 92 words by 8 bits

Contextual Info: SN74ALS232B 1 6 x 4 ASYNCHRONOUS FIRST IN, FIRST OUT MEMORY D3247 • Independent Asynchronous Inputs and Outputs DW OR N PACKAGE Package Options Include Plastic "Sm all O utline" Packages, Plastic Chip Carriers, and Standard Plastic 300-m il DIPs OE C TOP VIEW