MEGAFUNCTION Search Results

PCI-M32

Abstract: verilog code for MII phy interface
Contextual Info: Network Interface Features − Support for 10/100 Mbps data transfer rate MAC-PCI Ethernet MAC Controller with PCI Host Interface Megafunction − Media Independent Interface MII for 10/100 Mbps operation − Automated MII Management interface Data Link Layer Functionality

rc5 protocol

Abstract: EP2C5T144C6 RC5 encoder RC5 philips RC5 IR philips RC5 decoder philips RC5 protocol altera manchester RC5 decoder EP1C3T100C6
Contextual Info:  5-bit address and 6-bit com- mand length IR-RC5-E and -D Infrared Encoder and Decoder Megafunctions  Bi-phase coding also known as Manchester coding  Carrier frequency of 36 kHz as per the RC5 standard  Fully synchronous design Encoder Features

intel 8051 Arithmetic and Logic Unit -ALU

Abstract: Memory Management 8051 8051 address decoder verilog code for ALU implementation 80C31 80C51 ASM51 SAB80C537 verilog code for 32 BIT ALU implementation verilog code for 8051
Contextual Info:  Control Unit − Eight-bit instruction decoder for MCS 51 instruction set R8051XC-EP 8051-Compatible Microcontroller Megafunction An economical, entry-point, fixed-configuration megafunction that implements an 8051-like 8-bit microcontroller that executes all ASM51 instructions. It has the same instruction set as the 80C31, but executes operations an average of eight times faster.

EP1AGX50-6

Abstract: charge controller block diagram
Contextual Info: Compliant with PCI Local Bus Specification, Revision 2.3 66 MHz performance PCI clock frequency PCI-M64 64-bit datapath 64-bit/66MHz PCI Master/Target Interface Megafunction The PCI-M64 megafunction provides a fast, fully-featured, master/target interface that

verilog code for 32 bit AES encryption

Abstract: FIPS-197 SP800-38A EP3C40-6
Contextual Info: AES-P Programmable AES Encrypt/Decrypt Megafunction Conforms to the Advanced Encryption Standard AES standard (FIPS PUB 197) Single module efficiently integrates multiple AES functions and modes Run-time programmable for: − Encryption or Decryption − Cipher Key length:

HSCX 82525

Abstract: R8051XC-HDLC hdlc R8051XC
Contextual Info:  LAPB/LAPD controlling machine providing  modulo 8 frame numbering HDLC  modulo 128 frame numbering HDLC Protocol Controller Megafunction  automatically generated res-  one- or two-byte addressing ponses  Serial Peripheral Interfaces  Bit stuffing

jpeg encoder vhdl code

Abstract: vhdl code for dwt transform vhdl code for discrete wavelet transform EP2AGX190 EP2S90 EP3C55 EP4SGX70 JPEG2000 ip based cctv systems altera dwt image compression
Contextual Info: JPEG 2000 compliance Both lossless and lossy compression JPEG2K-E Error-resilient compression JPEG 2000 Encoder Megafunction Headers syntax processing The JPEG2K-E megafunction is a complete high performance JPEG2000 - ISO/IEC 15444-1 image compression solution targeted for video and high bandwidth image

rgb TO HDMI convert chip

Abstract: AD9889B CH7301C lcd qvga 320x240 Sitronix ST7787 ADV7120 RGB24 EP3C40-6 YCbCr TO TFT converter graphic lcd module 320x240
Contextual Info: Generates color and control data for standard displays in the following resolutions: DISPLAY-CTRL High-Resolution Display Controller Megafunction Implements a controller that accepts video data and works with a digital/analog converter DAC to drive standard QVGA (320x240) to WUXGA (1920x1200) displays.

Contextual Info:  Interfaces directly to Mobile and SDR-SDRAMCTRL Single Data Rate Mobile SDRAM Controller Megafunction ordinary Single Data Rate SDR SDRAM chips and registered/unbuffered DIMMS  Supports address space up to 2G (230 words) and – one to eight chip selects,

MAC-1G

Abstract: EP2S15-3 TLSM
Contextual Info: Network interface features o Supports data transfer rates of 10/100/1000 Mbps MAC-1G 1-Gigabit Ethernet Media Access Controller Megafunction o MII/GMII Media Independent Interface o Optional RMII, SMII o PHY management interface* Data link layer functionality

dct verilog code

Abstract: EP20K100E-1 2d dct block
Contextual Info: Ease of Integration & Performance  High clock speed >250 MHz in 0.18um ASIC technologies DCT  Low gate count 2-D Forward Discrete Cosine Transform Megafunction  Low latency (87 cycles)  Single clock cycle per sample operation Design Quality  Fully compliant with the JPEG

SpeedTags

Contextual Info: Scalado CAPSTM Compliance  Integrates SpeedTagsTM tech- nology SVE-JPEG-E JPEG Features SpeedView Enabled JPEG Encoder Megafunction  Programmable quantization  Programmable Huffman Tables two DC, two AC and tables (four)  Up to four color components

EPF10K100B

Abstract: EPF10K100E EPF10K130E EPF10K200E EPF10K30E EPF10K50E EPF10K50S
Contextual Info: FLEX 10KE Embedded Programmable Logic Devices March 2001, ver. 2.3 Data Sheet • Features. ■ ■ f Embedded programmable logic devices PLDs , providing system-on-a-programmable-chip (SOPC) integration in a single device – Enhanced embedded array for implementing megafunctions

EPF10K50S

Abstract: EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K30E EPF10K50E FLEX controller vhdl code
Contextual Info: FLEX 10KE Embedded Programmable Logic Family September 2000, ver. 2.10 Features. Data Sheet • ■ ■ f Embedded programmable logic devices PLDs , providing system-on-a-programmable-chip integration in a single device – Enhanced embedded array for implementing megafunctions

Contextual Info: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig Megafunctions AN-661-3.0 Application Note This application note describes the flow for implementing fractional phase-locked loop PLL reconfiguration and dynamic phase shifting for fractional PLLs in 28-nm

HDTV transmitter receivers block diagram

Abstract: 20 channel GRAPHIC EQUALIZER eureka pci 64 10 channel GRAPHIC EQUALIZER block diagram graphic equalizer image processing DSP asic sican dsp adsl typical "bit error rate" MPEG-4 decoder receiver ADSL Modem circuit diagram
Contextual Info: ¨ Megafunctions Selector Guide System-on-a-Programmable-Chip Solutions June 1999 Contents 2 Introduction to Altera Megafunctions 4 Digital Signal Processing Megafunctions 7 Communications Megafunctions 8 PCI & Other Bus Interface Megafunctions 10 Processor & Peripheral Megafunctions

crc verilog code 16 bit

Abstract: note on vhdl and verilog data types vhdl pid controller usb transmitter receiver verilog code pid controller free vhdl code download for pll interrupt controller verilog code download PID controller EPF10K20 verilog pid controller
Contextual Info: USB Function Controller Megafunction Solution Brief 24 Target Applications: Buses & Interfaces Family: FLEX 10K & FLEX 8000 Vendor: June 1997, ver. 1 Features • ■ ■ ■ ■ Fully compliant with universal serial bus USB 1.0 Specification Automatic hardware-managed protocol

iir filter applications

Abstract: digital IIR Filter verilog iir filter EPF10K50
Contextual Info: Biquad IIR Filter Megafunction Solution Brief 3 Target Application: Digital Signal Processing Family: FLEX 10K Vendor: Integrated Silicon Systems Ltd. 29 Chlorine Gardens BELFAST, BT9 5DL, Northern Ireland Tel. 44 1232-664-664 Fax 44 1232-669-664 E-mail Info@ISS-DSP.com

alt_iobuf

Abstract: ep3*SL150F1152C2 altera double data rate megafunction sdc UG-01032-4
Contextual Info: ALTDLL and ALTDQ_DQS Megafunctions User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Version: Document Date: 9.1 4.0 May 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

Contextual Info: ALTDQ_DQS2 Megafunction User Guide ALTDQ_DQS2 Megafunction User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01089-1.0 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, and specific device designations are trademarks and/or service marks of Altera Corporation in the U.S. and

SIIGX52006-1

Abstract: RECONFIG
Contextual Info: 5. Stratix II GX ALT2GXB_RECONFIG Megafunction User Guide SIIGX52006-1.4 Introduction The MegaWizard Plug-In Manager in the Quartus® II software creates or modifies design files that contain custom megafunction variations. These auto-generated MegaWizard files can then be instantiated in a design file.

Contextual Info: Evaluating AMPP & MegaCore Functions April 2001, ver. 2.0 Introduction Application Note 125 Altera and Altera Megafunction Partners Program AMPPSM partners offer a large selection of off-the-shelf megafunctions optimized for Altera devices. Designers can easily implement these parameterized blocks of

Contextual Info: GFS2020A GFS2020A GFS2020A 1 6 X 4 CAM WITHOUT MASK GENERAL DESCRIPTION: THE GFS2020A MEGAFUNCTION IS A 16-WORD BY 4-BIT CONTENT ADDRESSABLE MEMORY CAM . THIS MEGAFUNCTION IS FUNCTIONALLY IDENTICAL TO THE FAIRCHILD 100142 EXCEPT THAT IT HAS SIXTEEN WORDS INSTEAD OF FOUR AND IT HAS NO MASK FUNCTION. FOR A DETAILED

transistor N14

Abstract: 22p03 P28 Transistor p18 transistor
Contextual Info: CFB2020A CFB2020A CFB2020A 16x16 2's Complement Multiplier DESCRIPTION: CFB2020A is a 16-by-16 2's complement multiplier which generates a 32-bit product. By using a modified Booth algorithm, this megafunction gives a reasonable speed and gate count. LOGIC SYMBOL: