MASTER PROTOCOL Search Results

KEIL

Contextual Info: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.30 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation  Requires only two pins SDA and SCL to interface to I2C bus

Contextual Info: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.10 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation  Requires only two pins SDA and SCL to interface to I2C bus

Contextual Info: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.0 Features • Industry-standard NXP® I2C bus interface • Supports Slave, Master, Multi-Master and Multi-Master-Slave operation  Only two pins SDA and SCL required to interface to I2C bus

Contextual Info: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.20 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation  Requires only two pins SDA and SCL to interface to I2C bus

Contextual Info: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.1 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation  Requires only two pins SDA and SCL to interface to I2C bus

RNW RESISTOR

Abstract: arbitrage verilog code for I2C MASTER
Contextual Info: PSoC Creator Component Data Sheet I2C Master/Multi-Master/Slave 2.10 Features • Industry standard Philips® I2C bus interface • Supports Slave, Master, Multi-Master and Multi-Master-Slave operation • Only two pins SDA and SCL required to interface to I2C bus

Contextual Info: PCI 9060SD MAY 1996 VERSION 0.6 PCI Bus Master Interface Chip for Master and Slave Adapters General Description _ Featu res_ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and slave adapters

Contextual Info: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 2.20 Features • Industry standard Philips® I2C bus interface • Supports Slave, Master, Multi-Master and Multi-Master-Slave operation    Only two pins SDA and SCL required to interface to I 2C bus

pci core

Abstract: Soft Core RTL FIFO synchronous fifo design in verilog
Contextual Info: PCI Peripheral Core PCI ADOUT Register Core Block Diagram PCI Parity Multiplexer Register Master Write FIFO PCI Bus Register Master Read FIFO Master State Machine/ DMA Register Master Request FIFO Output Mux Application Interface PCI I/O Cells ▼ Configuration

82355

Abstract: 29025
Contextual Info: IF^IlDMDRyw intei 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed for use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three Interfaces (EISA, Local CPU, and Transfer Buffer) Supports Automatic Handling of Complete EISA Bus Master Protocol

Contextual Info: PCI 9060SD T E C H N □ L □ EY November 1995 PRELIMINARY VERSION 0.5 PCI Bus Master Interface Chip for Master and Slave Adapters General Description_ Featu res_ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and

iso 4903

Abstract: 9060SD I960CX PCI9060SD
Contextual Info: PCI 9060SD T E C H N D L Q B Y MAY 1996 VERSION 0.6 PCI Bus Master Interface Chip for Master and Slave Adapters Feat u res_ General Description _ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and

Application Notes

Abstract: AVR32109 Master sequence device I2C TWI AVR32107 AVR32
Contextual Info: AVR32107: Using TWI as a Master on the AVR32 Features - Compatible with Philips' I2C protocol Master transmitter mode Master receiver mode 7-bit slave address – up to 127 devices on the same bus Normal 100kbps and Fast (400kbps) operation Interrupt driven communication

C500-ZL3AT1-E

Abstract: SRM1-C01-V1 CQM1-PRO01-E C200H-PRO27-E SRM1-C02-V1 SRM1-C01 ladder diagram
Contextual Info: Master Control Unit SRM1-C01-V1/C02-V1 Subminiature, Stand-alone Model with CompoBus/S Master and SYSMAC Controller Functions Maximum number of Remote I/O points per Master: 256 Maximum number of Slaves per Master: 32 Communications cycle time: 0.5 or 0.8 ms

82355

Contextual Info: 82355 The 82355 Bus Master Interface Controller BMIC is a highly integrated Bus Master designed for use in 32-Bit EISA Bus Master expansion board designs and supports all of the enhancements defined in the EISA specifications required for EISA bus master ap­

Contextual Info: VSB 1400 Æ X - VSB Master Module Interface Device Tu May 1989_ Distinctive Features_ Applications_ • Bus interface circuitry for multi-master VSB systems • VSB master chip contains - Single level arbiter

eeprom 24c04

Abstract: 014b signetics 24C04 24CXX 24LC01 24LC04 AN554 PIC16C64 PIC16C71 PIC16C74
Contextual Info: Software Implementation of I2C Bus Master AN554 Software Implementation of I2C Bus Master In most systems the microcontroller is the master and the external peripheral devices are slaves. In these cases this application note can be used to attach I2C slaves to the PIC16CXX the master microcontroller.

Contextual Info: Æ X - VSB 1400 T• VSB Master Module Interface Device May 1989_ Distinctive Features_ Applications_ • Bus interface circuitry for multi-master VSB systems • VSB master chip contains - Single level arbiter

RS-232 to i2c converter

Abstract: i2c to RS-232 converter SC18IM700 FPGA with i2c eeprom RS-232 chip to i2c converter RS-232 to spi converter SC18IM700IPW SC18IS600 SC18IS600IPW SC18IS601
Contextual Info: NXP I2C master bridges SC18IS600/601 and SC18IM700 Low-power bridges for SPI slave or UART to I2C master or GPIO These compact protocol converters create seamless, low-power, low-voltage interface connections, so they make it quick and easy to add I2C master and GPIO capability to any

VIC068A

Abstract: 68020 motorola
Contextual Info: 1.5 VIC068A VMEbus Master Operations The transfer of data is initiated by a VMEbus master module. The master module controls the type of transfer read, write, interrupt acknowledge, etc. and provides the address and address modifiers for the transfer. The timing of the start of the transfer is also controlled by the master.

9541A

Abstract: I2C-bus specification 3 HVQFN16 JESD22-A114 JESD22-A115 JESD78 TSSOP16 PCA9541AD-01 PCA9541A
Contextual Info: PCA9541A 2-to-1 I2C-bus master selector with interrupt logic and reset Rev. 03 — 16 July 2009 Product data sheet 1. General description The PCA9541A is a 2-to-1 I2C-bus master selector designed for high reliability dual master I2C-bus applications where system operation is required, even when one master

9541A

Abstract: PCA9541A
Contextual Info: PCA9541A 2-to-1 I2C-bus master selector with interrupt logic and reset Rev. 4 — 24 August 2012 Product data sheet 1. General description The PCA9541A is a 2-to-1 I2C-bus master selector designed for high reliability dual master I2C-bus applications where system operation is required, even when one master

Contextual Info: SCANSTA101 SCANSTA101 Low Voltage IEEE 1149.1 System Test Access STA Master Literature Number: SNLS057I SCANSTA101 Low Voltage IEEE 1149.1 System Test Access (STA) Master General Description Features The SCANSTA101 is designed to function as a test master

JESD22-A114

Abstract: JESD22-A115 JESD78 PCA9541 TSSOP16 PCA9541A
Contextual Info: PCA9541A 2-to-1 I2C-bus master selector with interrupt logic and reset Rev. 02 — 4 June 2009 Product data sheet 1. General description The PCA9541A is a 2-to-1 I2C-bus master selector designed for high reliability dual master I2C-bus applications where system operation is required, even when one master