MA9007 Search Results

54175

Contextual Info: GEC P L E S S E Y M S E M I C O N D U C T O R S DS3594-3.3 54HSC/T Series RADIATION HARD HIGH SPEED CMOS/SOS LOGIC The CMOS/SOS HSC/T Series offer the combined benefits of low power, high speed CMOS with the inherent latch up immunity, Single Event Upset SEU immunity and the high

figure of full adder circuit using nor gates

Abstract: tristate buffer cmos LAH3 carry select adder 16 bit using fast adders full adder circuit using nor gates microprocessor radiation hard M2909
Contextual Info: Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ MA9000 Series

16-LINE TO 4-LINE PRIORITY ENCODERS

Abstract: t04 68 3 pin diode t04 68 3 pin transistor EB 36 3C GR "silicon on sapphire" 74 LS 04 Logic Gates cmos dual s-r latch MIL-STD-38510 multiplexers 74 LS 150 transistor T04
Contextual Info: 54HSC/T Series 54HSC/T Series Radiation Hard High Speed CMOS/SOS Logic Replaces May 1995 version, DS3594-3.3 The CMOS/SOS HSC/T Series offer the combined benefits of low power, high speed CMOS with the inherent latch up immunity, Single Event Upset SEU immunity and the high

Contextual Info: GEC PLESSEY DS3598-3.4 MA9000 Series SILICON-ON-SAPPHIRE RADIATION HARD GATE ARRAYS The logic building block for the GPS double level metal C M O S /S O S ga te arrays is a fo u r tra n s is to r ‘c e ll-u n it’ equivalent in size to a 2 input NAND gate. Back to back cellunits as illustrated, organised in rows, form the core of the

full adder circuit using nor gates

Abstract: D-latch DIL40 DIL48 half adder ttl half adder circuit using nor and nand gates microprocessor radiation hard datasheet SRDL DIL14 DIL16
Contextual Info: MA9000 Series MAY 1995 DS3598-3.4 MA9000 Series SILICON-ON-SAPPHIRE RADIATION HARD GATE ARRAYS The logic building block for the GPS double level metal CMOS/SOS gate arrays is a four transistor ‘cell-unit’ equivalent in size to a 2 input NAND gate. Back to back cellunits as illustrated, organised in rows, form the core of the

LAH3

Abstract: LAH4 MA9000 Inverter INVC fpk6
Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS MA9000 Series MAY 1995 DS3598-3.4 MA9000 Series SILICON-ON-SAPPHIRE RADIATION HARD GATE ARRAYS The logic building block for the GPS double level metal CMOS/SOS gate arrays is a four transistor ‘cell-unit’

M2909

Contextual Info: GEC PLESSEY S 1M I C \ 1) 1; ( . MA9000 Series Silicon-on-Sapphire Radiation Hard Gate Arrays ] () K > S21300FDS Issue 1.1 November 1990 Features Cell Unit • Radiation Hard to 1MRad(Si) V DD ^ I • High SEU immunity, latch-up free • Double-Level-Metal CMOS/SOS Technology