M-BITS FIFO FIELD MEMORY Search Results

Brooktree Bt878

Abstract: logitech x 530 BT878 sony KSS 121 sony KSS 123 alps i2c tuner INTEL Core i5 760 NTSC 640x480 CCIR601 CCIR656
Contextual Info: Functional Overview The Bt879 video and audio capture chip is a multi-function Peripheral Component Interconnect PCI device intended for +5 V only operation. The video function features a Direct Memory Access (DMA)/PCI bus master for analog NTSC/PAL/SECAM composite, S-Video, and digital CCIR656 video capture. The

Contextual Info: F u n c t io n a l D e s c r ip t io n Functional Overview Video Capture Over PCI Bus The Bt848/848A/849A integrates an NTSC/PAL/SECAM composite & S-Video decoder, scaler, DM A controller, and PCI Bus master on a single device. Bt848/848A/849A can place video data directly into host memory for video cap­

82750db

Contextual Info: irrte1 82750PB PIXEL PROCESSOR 25 MHz Clock with Single Cycle Execution Pixel Interpolator 512 x 48-Bit Instruction RAM High Performance Memory Interface — 32-Bit Memory Data Bus — 50 MBytes per Second Maximum — 25 MBytes per Second with Standard VRAMs or DRAMs

d4564163

Abstract: d4564163-a80 Am29LV065D-120R AM29LV065D NEC D4564163-A80 MT48LC2M32B2 sdram chip EP2S60F672C5 MT48LC4M32B2 NII51005-7
Contextual Info: Section I. Memory Peripherals This section describes memory components and interfaces provided by Altera . These components provide access to on-chip or off-chip memory for SOPC Builder systems. See About This Handbook for further details. This section includes the following chapters:

Contextual Info: GT-64060 IBBIBk « Galileo !»; Technology High-lntegration PCI Bridge/ Memory Controller P roduct Preview R evision 0.7 4/1/97 Please contact Galileo Technology for possible updates before finalizing a design. FEATURES • High-integration PCI bridge/memory controller with

Contextual Info: Standard Products UTCAM-EngineTM Dynamically Configurable Content Addressable Memory Engine Preliminary Datasheet Nov. 1998 FEATURES External Memory q Addresses up to 8 mega words of SSRAM Performance and Flexibility q Rapid association matching for exact match seeks

Scatter-Gather direct memory access SG-DMA

Abstract: memory access (DMA) controller Scatter-Gather CRC-32 QII55003-7 constructs
Contextual Info: 5. Scatter-Gather DMA Controller Core QII55003-7.1.0 Core Overview The Scatter-Gather direct memory access SG-DMA controller core implements high-speed data transfer between two devices. The SG-DMA core can be used to transfer data from: • ■ ■ memory to memory

VRC4375

Abstract: ROE EG Series R4300 VR4300TM Motorola F245 NEC VR4300
Contextual Info: VRC4375 System Controller Data Sheet August 2000 Description The VRC4375TM system controller is a software-configurable chip that interfaces directly with an NEC VR43xxTM 64-bit MIPS RISC CPU and PCI bus without external logic or buffering. The system controller also interfaces with memory SDRAM, EDO, fast-page

u2064

Contextual Info: Standard Products UTCAM-EngineTM LPM Dynamically Configurable Content Addressable Memory Engine with Longest Prefix Match Preliminary Datasheet June 1999 FEATURES External Memory q Addresses up to 32 gigabytes of memory q Can drive either SSRAM or SDRAM Host Interface

F245A

Abstract: UPD4564421 italiana 2000V F244 F245 R4300 VR4300 VR4300TM VRC4373 80 lead flash simm programmer
Contextual Info: V 4373 System Controller RC Data Sheet October 1997 1.0 Introduction 1.1 The VRC4373TM system controller is a software-configurable chip that directly interfaces the VR4300TM CPU and PCI bus without external logic or buffering, and also interfaces memory SDRAM, EDO, fast-page DRAM, and flash boot ROM with minimal buffering. From the viewpoint of the VR4300 CPU, the VRC4373 acts as a memory controller,

MCF5272UM

Contextual Info: MCF5272 ColdFire Integrated Microprocessor User’s Manual ColdFire® Microcontrollers MCF5272UM Rev. 3 03/2007 freescale.com Overview 1 ColdFire Core 2 Hardware Multiply/Accumulate MAC Unit 3 Local Memory 4 Debug Support 5 System Integration Module (SIM)

8002B

Abstract: isc Instruction X0848 Brooktree Bt848 tv tuner
Contextual Info: Advance Information Bt848 is a complete, low cost single-chip solution for analog N T S C / P A L / S E C A M video capture on the P C I bus. As a bus master, Bt848 does not require any local memory buffers to s:ore video pixel data which signifi­ cantly minimizes the hardware cost for this architecture. Bt848 takes advantage

ALCATEL PABX

Abstract: 2028x MTC-20280 MTC-20270 wildcard 88 16650 uart baudrate diode A612 MTC-20276 MTC20277 mtc-20277
Contextual Info: MTC-20280 ISDN/IDSL Terminal Controller Data Sheet Preliminary Rev 2.0 November 1998 Key Features Key Applications General Description ▼ Integrated ARM7TDMI RISC processor core ▼ 16 or 8 bit memory bus ▼ 3, full-duplex HDLC formatters with FIFO ▼ 3-way GCI interface and

Contextual Info: D M A C O N TR O LLE R 8.1 AMDÌ1 O V E R V IE W Direct memory access DMA permits the transfer of data between memory and peripherals without CPU involvement. With DMA transfers, the DMA controller becomes the bus master. The arbitration for the bus is internal to the processor and is not visible externally. When

RM0006

Abstract: F423 STR91XF system tick tachogenerator and universal motor transistor f423 TV11 tv11 capacitor STR9 flash programming ccx 1013 Philips F423
Contextual Info: RM0006 Reference manual STR91xFA ARM9 - based microcontroller family Introduction This reference manual provides complete information for application developers on how to use the STR91xFA microcontroller memory and peripherals. The STR91xFA is a family of microcontrollers with different memory sizes, packages and

CY7C09449PVA-AC

Abstract: 8c04 i486 PC MOTHERBOARD CIRCUIT diagram
Contextual Info: CY7C09449PVA-AC 128 Kb Dual-Port SRAM with PCI Bus Controller PCI-DP Features Functional Overview • 128 Kb of dual-ported shared memory ■ Master and target PCI Specification 2.2 compliant interface ■ Embedded host bridge capability ■ Direct interface to many microprocessors

18320

Contextual Info: IDT72V15160 IDT72V16160 IDT72V17160 IDT72V18160 IDT72V19160 3.3V MULTIMEDIA FIFO 16 BIT V-III, 32 BIT Vx-III FAMILY UP TO 1 Mb DENSITY • • • FEATURES: • • • • Choose among the following memory organizations: Commercial • V-III Vx-III IDT72V15160 - 4,096 x 16

Contextual Info: CP3UB17 CP3UB17 Reprogrammable Connectivity Processor with USB Interface Literature Number: SNOSA99C CP3UB17 Reprogrammable Connectivity Processor with USB Interface 1.0 General Description The CP3UB17 connectivity processor combines a powerful RISC core with on-chip SRAM and Flash memory for high

alcatel 1511 mux

Contextual Info: TitlePage - 80A5000_MA001_05 PowerPro CA91L750 PowerPC Memory Controller Manual www.tundra.com Trademarks Tundra and the Tundra logo are registered trademarks of Tundra Semiconductor Corporation (“Tundra”). All other trademarks, services marks and logos (“Marks”) are the property of their respective holders including Tundra. Users are not

a2431

Abstract: PPB2 C1995 DP8466B DP8466BN-12 DP8466BN-20 DP8466BN-25 DP8466BV-12 N48A ST506
Contextual Info: DP8466B Disk Data Controller General Description Features The DP8466B Disk Data Controller DDC is an intelligent peripheral which interfaces Winchester or Floppy disk drives to microprocessor based systems It transfers data between a buffer memory or host system and the serial bit data

Contextual Info: LogiCORE IP Multi-Port Memory Controller v6.06.a DS643 February 22, 2013 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Multi-Port Memory Controller (MPMC) is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2/DDR3/LPDDR

nand flash ecc bits

Abstract: arbiter decoder -1996 M-Bits FIFO Field Memory FLASH DRIVE CONTROLLER intel 80c188
Contextual Info: ABRIDGED VERSION / il SSI 36C3950 s é c o n M PCMCIA-ATA/IDE Flash Drive Controller Ìa n s A TDK Group/Company Advance Information February 1996 FEATURES DESCRIPTION The SSI 36C3950 ATA FLASH Controller is a CMOS monolithic integrated circuit housed in a 144-lead

310ERF

Abstract: alcatel 1648
Contextual Info: TitlePage - 80A5000_MA001_08 PowerPro PowerPC Memory Controller User Manual Document Number: 80A5000_MA001_08 Document Status: Final Release Date: October 2002 This document discusses the features, capabilities, and configuration requirements of the PowerPro. It is intended for

PID microcontroller

Abstract: 1766B "USB" peripheral
Contextual Info: Features • • • • • • • • USB V1.1-Compliant/12 Mbits/s Number and Size of Endpoints Fully Parametrizable in RTL Embedded Dual-port RAM for Endpoints Suspend/Resume Logic Ping-pong Mode 2 Memory Banks for Isochronous Endpoints Compatible with Any 8-bit Microcontroller