M-BITS FIFO FIELD MEMORY Search Results

R22A

Contextual Info: Standard Products UTCAM-Engine Dynamically Configurable Content Addressable Memory Engine Preliminary Datasheet Oct. 19, 1998 FEATURES External Memory Host Interface Q Q Addresses up to 32 gigabytes of memory Q Can drive either SSRAM or SDRAM Performance and Flexibility

BPK72

Abstract: intel 7110 DMA Controller 8257 isbx-251
Contextual Info: APPLICATION NOTE AP-157 O c to b e r 1983 AP-157 INTRODUCTION^ The 7220-! is a single-chip LSI Bubble Memory Controller BMC that implements a bubble memory storage subsystem (with up to eight bubble storage units (BSUs) per BMC). Each bubble storage unit consists of five support circuits in addition

Brooktree Bt878

Abstract: logitech x 530 BT878 sony KSS 121 sony KSS 123 alps i2c tuner INTEL Core i5 760 NTSC 640x480 CCIR601 CCIR656
Contextual Info: Functional Overview The Bt879 video and audio capture chip is a multi-function Peripheral Component Interconnect PCI device intended for +5 V only operation. The video function features a Direct Memory Access (DMA)/PCI bus master for analog NTSC/PAL/SECAM composite, S-Video, and digital CCIR656 video capture. The

Contextual Info: F u n c t io n a l D e s c r ip t io n Functional Overview Video Capture Over PCI Bus The Bt848/848A/849A integrates an NTSC/PAL/SECAM composite & S-Video decoder, scaler, DM A controller, and PCI Bus master on a single device. Bt848/848A/849A can place video data directly into host memory for video cap­

om 355 engine

Contextual Info: Standard Products UTCAM-Engine LPM Dynamically Configurable Content Addressable Memory Engine with Longest Prefix Match Preliminary Datasheet May 1999 :I g ». O I Ik I » f I <8 M i & ¥ » U M S FEATURES Host Interface External Memory Q Q Addresses up to 32 gigabytes of memory

rspo5

Contextual Info: 4.0 DATA STRUCTURE 4.1 ADDRESS MAP The NHI-RT appears to the host as 4K words o f memory divided into the following blocks: Address Range 0 - 29 Description Internal Control and Status registers 30 External RT address / Command output pins 31 I/O tag word

Z7220A

Abstract: RF2065 128X14 LT 7220
Contextual Info: Zilog October 1988 D escription The Z7220A High-performance Graphics Display Con­ troller HGDC is an intelligent microprocessor peripheral designed to be the heart of a high-performance rasterscan computer graphics and character display system. Positioned between the video display memory and the

Z7220A

Abstract: algorithm behind 5 pen pc technology 5 PEN PC TECHNOLOGY advance Z7220 LT 7220 HA-12 OA-16 raster timing 5 PEN PC TECHNOLOGY OAD 13
Contextual Info: Zilog October 1988 D escription The Z7220A High-performance Graphics Display Con­ troller HGDC is an intelligent microprocessor peripheral designed to be the heart of a high-performance rasterscan computer graphics and character display system. Positioned between the video display memory and the

82750db

Contextual Info: irrte1 82750PB PIXEL PROCESSOR 25 MHz Clock with Single Cycle Execution Pixel Interpolator 512 x 48-Bit Instruction RAM High Performance Memory Interface — 32-Bit Memory Data Bus — 50 MBytes per Second Maximum — 25 MBytes per Second with Standard VRAMs or DRAMs

Intel 82750

Abstract: 82750DB 82750 82750PB 82750PA DVI 82750DB 3D214 BC 827 vram dual port intel DOC
Contextual Info: in y 82750PB PIXEL PROCESSOR Pixel Interpolator 25 MHz Clock with Single Cycle Execution 512 x 48-Bit Instruction RAM High Performance Memory Interface — 32-Bit Memory Data Bus — 50 MBytes per Second Maximum — 25 MBytes per Second with Standard VRAMs or DRAMs

d4564163

Abstract: d4564163-a80 Am29LV065D-120R AM29LV065D NEC D4564163-A80 MT48LC2M32B2 sdram chip EP2S60F672C5 MT48LC4M32B2 NII51005-7
Contextual Info: Section I. Memory Peripherals This section describes memory components and interfaces provided by Altera . These components provide access to on-chip or off-chip memory for SOPC Builder systems. See About This Handbook for further details. This section includes the following chapters:

Contextual Info: GT-64060 IBBIBk « Galileo !»; Technology High-lntegration PCI Bridge/ Memory Controller P roduct Preview R evision 0.7 4/1/97 Please contact Galileo Technology for possible updates before finalizing a design. FEATURES • High-integration PCI bridge/memory controller with

C-Cube VRP3

Contextual Info: 8 CLM4550 Broadcast API Features Access This chapter describes the protocols and memory locations used to access the broadcast API features of the CLM4550. The sections in this chapter are: • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 8.1, CLM4550 Broadcast Interface

intel 8259 programmable interrupt controller

Abstract: TCDF 1900 Memtech d7225 Bubble Memory 7225 bubble D7225-6 kz3C D7225-1 8257 functional diagram
Contextual Info: M e m /e c h ^ 7225 CONTROLLER FOR 4-MEGABIT BPK 74 BUBBLE MEMORY SUBSYSTEM 0°C to + 70CC —40°C to + 85°C D7225-1 D7225-6 Three Modes of Data Transfer — DMA — Polled — Enhanced Interrupt Transfer of Single 64 bytes or Multiple Pages of Data System Power Fail Protection Internally

free stk ic

Contextual Info: XL-8220 PROCESSOR DATA BOOK PRELIMINARY DATA March 1990 Chapter 1. Overview 1.1. Features C O ST -EFFEC T IV E P R IN TE R PR O C ESSO R IN T EG R A TED SY ST EM FU N C T IO N S 32-bit RISC processor for PostScript-language page printers Zero-glue D R A M memory controller

d2091

Abstract: uPD65948S1-068 f245 motorola VRC4375 F245-type CL-GD5465 National Semiconductor PC16550D UART VR43xx R4300 VR4300TM
Contextual Info: VRC4375 System Controller Preliminary Data Sheet October 1999 Description The VRC4375TM system controller is a software-configurable chip that interfaces directly with an NEC VR43xxTM 64-bit MIPS RISC CPU and PCI bus without external logic or buffering. The system controller also interfaces with memory SDRAM, EDO, fast-page

0xf6000

Abstract: C-Cube VRP3
Contextual Info: 9 CLM4400 Broadcast API Features Access This chapter describes the protocols and memory locations used to access the broadcast API features of the CLM4400. The sections in this chapter are: • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 9.1, CLM4400 Broadcast Interface

ICS RS 3197

Abstract: ntsc to rgb SAA7196 philips type 3186 capacitor AD15/117 SAA7116 SAA7116H video data in planar YUV format 1994 AD9129 SAA7110
Contextual Info: P hilips Sem iconductors Desktop Video Products P relim inary specification Digital vid eo to PCI interface FEATURES GENERAL DESCRIPTION • 1024 byte FIFO memory size • Full multistandard video input capability with Philips Video Decoder Chipset • Image resolution up to 768 x 576 (full PAL

Contextual Info: Standard Products UTCAM-EngineTM Dynamically Configurable Content Addressable Memory Engine Preliminary Datasheet Nov. 1998 FEATURES External Memory q Addresses up to 8 mega words of SSRAM Performance and Flexibility q Rapid association matching for exact match seeks

STR S 6307

Abstract: str 6307 uP 6308 AD STR 6309 STR 6307 POWER uP 6308 AP str s 6309 LT 7224 of str 6309 str 6308
Contextual Info: 7224 CONTROLLER FOR 4MBIT BPK 5V74 BUBBLE MEMORY SUBSYSTEM • Provides Interface between Host Microprocessor and 4 Mbit Bubble Memory Subsystems ■ 18 Easy-to-Use Commands . Three Modes of Data Transfer _ ■ Interlaces to 8080/85/86/88/186/286 and Other Standard Microprocessors

8086 8257 DMA controller interfacing

Abstract: interfacing of 8257 devices with 8085 interfacing of 8257 with 8086 interfacing of 8237 with 8086 IC AN 7220 IC AN 7220 b interfacing of 8237 with 8085 8086 8257 DMA controller intel 8085 pin assignments ic dma 8237 8088
Contextual Info: in te T MSWMKSIS ONIFOäßMirO ßO 7220 BUBBLE MEMORY CONTROLLER • DMA Handshake Capability 8080/8085/8088/8086 Microprocessor Interface ■ Single or Multiple Page Block Transfers Interfaces Up to Eight Bubble Storage Subsystems ■ HMOS Technology ■ Standard 40-Pin Dual In-Line Package

dma 8257

Abstract: BPK-72 Bubble Memory IC AN 7220 Bubble Memory BPK72 Memtech intel 8257 7220 DMA Controller 8257 IC AN 7220 b
Contextual Info: M em /e c h 7220 CONTROLLER FOR 1 MBIT BPK 70 AZ BUBBLE MEMORY SUBSYSTEM 0°C To 75°C —20°C To + 85°C —40°C To +85°C 7220-1 7220-5 7220-6 • Provides Interface between Host Microprocessor and 1 Mbit Bubble Subsystems ■ 16 Easy-to-Use Commands ■ Interfaces to 8080/85/86/88/186/286

Z86E122

Abstract: Z86E126 transistor 1240 f3h E125 g diode e136pz
Contextual Info: The MUZE Family of Z8 Microcontrollers MAXIMUM MEMORY WITH UART AND ZILOG EXPANDABLE EPROM Product Specification PRELIMINARY PS004005-1100 ZiLOG Worldwide Headquarters • 910 E. Hamilton Avenue • Campbell, CA 95008 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com

Scatter-Gather direct memory access SG-DMA

Abstract: memory access (DMA) controller Scatter-Gather CRC-32 QII55003-7 constructs
Contextual Info: 5. Scatter-Gather DMA Controller Core QII55003-7.1.0 Core Overview The Scatter-Gather direct memory access SG-DMA controller core implements high-speed data transfer between two devices. The SG-DMA core can be used to transfer data from: • ■ ■ memory to memory