M 1667 Search Results

Contextual Info: CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBLTM Architecture Functional Description Features • Pin-compatible and functionally equivalent to ZBT™

cy7c1470v25

Contextual Info: CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBLTM Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™

Contextual Info: CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT

Contextual Info: CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBLTM Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™

Contextual Info: - Technical Data File N um b er 1667 CD54/74HC109 C D54/74HCT109 High-Speed CMOS Logic Duai J-K Flip-Flop with Set and Reset Type Features: 9 2 C S -36532 • Positive-Edge triggered • A s y n c h ro n o u s S et a n d Reset m 60 M Hz Typical M axim um C lo ck Frequency

cy7c1441av33-133axi

Abstract: R1136 CY7C1441
Contextual Info: CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 36-Mbit 1 M x 36/2 M × 18/512 K × 72 Flow-Through SRAM 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Flow-Through SRAM Features Functional Description • Supports 133-MHz bus operations ■ 1 M × 36/2 M × 18/512 K × 72 common IO

Contextual Info: CY7C1460AV25 CY7C1462AV25 36-Mbit 1 M x 36/2 M × 18 Pipelined SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™

CY7C1470BV25

Contextual Info: CY7C1470BV25 CY7C1472BV25 72-Mbit 2 M x 36/4 M × 18 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™

Contextual Info: CY7C1460AV25 CY7C1462AV25 36-Mbit 1 M x 36/2 M × 18 Pipelined SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™

Contextual Info: CY7C1460AV33 CY7C1462AV33 36-Mbit 1 M x 36/2 M × 18 Pipelined SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT ■

Contextual Info: CY7C1461AV33 CY7C1463AV33 36-Mbit 1 M x 36/2 M × 18 Flow-Through SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead

Contextual Info: CY7C1480BV33 CY7C1482BV33 72-Mbit 2 M x 36/4 M × 18 Pipelined Sync SRAM 72-Mbit (2 M × 36/4 M × 18) Pipelined Sync SRAM Functional Description Features • Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■

Contextual Info: CY7C1471BV33 CY7C1473BV33 72-Mbit 2 M x 36/4 M × 18 Flow-Through SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture Functional Description Features • No bus latency™ (NoBL™) architecture eliminates dead cycles

Contextual Info: CY7C1480BV33 CY7C1482BV33 72-Mbit 2 M x 36/4 M × 18 Pipelined Sync SRAM 72-Mbit (2 M × 36/4 M × 18) Pipelined Sync SRAM Features Functional Description • Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■

408-1379

Abstract: AMP catalog 82003 komax 433 nas 7103 KOMAX 333 operating instructions komax 200277-2 201355-1 201692-4 21393
Contextual Info: RoHS Ready M Series Pin and Socket Connectors AMP M Series Pin and Socket Connectors NOTE: All part numbers are RoHS Compliant M Series Connectors Product Facts • Most connectors intermateable with connectors made to MIL-C-28748 requirements Standard Housings

Contextual Info: CY7C1441AV25 CY7C1447AV25 36-Mbit 1 M x 36/512 K × 72 Flow-Through SRAM 36-Mbit (1 M × 36/512 K × 72) Flow-Through SRAM Functional Description Features • Supports 133 MHz bus operations ■ 1 M × 36/512 K × 72 common I/O ■ 2.5 V core power supply

Contextual Info: CY7C1481BV33 72-Mbit 2 M x 36 Flow-Through SRAM 72-Mbit (2 M × 36) Flow-Through SRAM Features Functional Description • Supports 133 MHz bus operations ■ 2 M × 36 common I/O ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O supply (VDDQ) ■

Contextual Info: CY7C1441AV33 36-Mbit 1 M x 36 Flow-Through SRAM 36-Mbit (1 M × 36) Flow-Through SRAM Features Functional Description • Supports 133-MHz bus operations ■ 1 M × 36 common I/O ■ 3.3 V core power supply ■ 2.5 V or 3.3 V I/O power supply ■ Fast clock-to-output times

Contextual Info: CY7C1381D CY7C1383D, CY7C1383F 18-Mbit 512 K x 36/1 M × 18 Flow-Through SRAM 18-Mbit (512 K × 36/1 M × 18) Flow Through SRAM Features Functional Description • Supports 133 MHz bus operations ■ 512 K × 36 and 1 M × 18 common I/O ■ 3.3 V core power supply (VDD)

AMP 169341-1

Abstract: G6506
Contextual Info: A M P triirAj».‘MUO-,i 11 I A MIIM ,o llA N 1 ' uv • • • A PPLICATIO N AND M AINTENANCE FO B AMP" HAND CRIM PIN G TO O L 169341-1 Sectio n I o f ¡his instruction sheet provides application procedures for A M P hand crim ping tools. I if.swucuwSn^

dda006

Abstract: TIC 33 LCD STK 5331 TK68HC711 68HC11K TK68HC711KS2 68HC11KS8 PB1AD
Contextual Info: TK68HC11KTK68H C11KTK68HC11KT 8HC11KTK68HC11 C11KTEKMOSTK68 K68HC11KTK68HC 1KTK68HC11KTK6 C11KTK68HC11KT TK68HC11KTK68H TK68HC11K Family Technical Data Te k m o s Your Trusted Manufacturer for Semiconductors TK68HC11K Te k m o s Your Trusted Manufacturer for Semiconductors

Contextual Info: HA16671MP, HA16672MP Voice Coil M otor VCM Servo C ontroller Description The H A 1 6 6 7 IM P and H A 1 6 6 7 2 M P are V C M ser v o controllers for hard disk head positioning. Three chips can make up a control system for the HA 13447 VCM driver: the H A 1 6 6 7 0 M P fo r p o s itio n s ig n a l g e n e r a tio n , and the

MD 7144

Contextual Info: Preliminary W42B974 ill# ICW0RKS 3.3/5.0V PLL Clock Driver Features Functional Selections Pin for pin com patible with M otorola MPC974 Parameter 15 LVCM OS/LVTTL clock outputs Reference/Status VCO Selection Internal PLL circuit allows input frequency m ultiplication

Contextual Info: CY7C1370D, CY7C1372D 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture Functional Description Features • Pin-compatible and functionally equivalent to ZBT™