LVDS 20 PIN TO 30 PIN Search Results

Contextual Info: UVVJ Series 5x7 mm, 3.3 Volt, LVPECL/LVDS, VCXO • Integrated phase jitter of less than 1 ps from 12 kHz to 20 MHz • Ideal for 10 and 40 Gigabit Ethernet and Optical Carrier applications Pin Connections 30 UVVJ Series 5x7 mm, 3.3 Volt, LVPECL/LVDS, VCXO

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Abstract: ICS843S2807 ICS843S2807BY MS-026 Nippon capacitors
Contextual Info: PRELIMINARY ICS843S2807 FEMTOCLOCK CRYSTAL-TOLVPECL/LVDS/LVCMOS CLOCK GENERATOR • Maximum output frequency: 350MHz VCCO_LVCMOS QA0 VEE QB1 • Crystal input frequency: 25MHz QB0 PIN ASSIGNMENT VCCO_LVCMOS • Five banks of outputs: Bank A: one single-ended QA0 LVCMOS output at: 133MHz

Contextual Info: V386 8-BIT LVDS RECEIVER FOR VIDEO General Description Features The V386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.38 Gbps throughput or 297.5 Mbytes per second. • Pin and function compatible with the National

SN65LVDS1224

Abstract: LVDS Serializer MO-150 SN65LV1023 SN65LV1023DB SN65LV1224 SN65LV1224DB SN65LVDS1023
Contextual Info: SN65LV1023/SN65LV1224† 30 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527B – FEBRUARY 2002 – REVISED APRIL 2002 D D D D 300–660 Mbps Serial LVDS Data Payload Bandwidth at 30 MHz to 66 MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224

Contextual Info: SN65LV1023/SN65LV1224† 30 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527C – FEBRUARY 2002 – REVISED MAY 2002 D D D D 300–660 Mbps Serial LVDS Data Payload Bandwidth at 30 MHz to 66 MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224

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Abstract: SI5334A Si5334C-Axxxxx-GM JESD78 Si5334 SSTL-18 Si5334B-Axxxxx-GM SI5334D
Contextual Info: Si5334 P I N - C ONTR OLLED A N Y - F REQUENCY, A NY - O UTPUT Q U A D C L O C K G ENERATOR Features Applications Si5334 Transparent Top View OEB  Pin Assignments VDDO0  Ordering Information: See page 24. CLK0B  CLK0A  Independent output voltage per

DS15BR400

Abstract: AN1194 DS15BR400EVK DS15BR401 TQFP-48
Contextual Info: DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description Features The DS15BR400/DS15BR401 are four channel LVDS buffer/ repeaters capable of datarates of up to 2 Gbps. High speed data paths and flow-through pinout minimize internal device

DS15BR400

Abstract: DS15BR400EVK AN-1194 DS15BR401 TQFP-48
Contextual Info: DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description Features The DS15BR400/DS15BR401 are four channel LVDS buffer/ repeaters capable of datarates of up to 2 Gbps. High speed data paths and flow-through pinout minimize internal device

Contextual Info: SN65LV1023/SN65LV1224 30 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527A – FEBRUARY 2002 – REVISED APRIL 2002 D D D D 300–660 Mbps Serial LVDS Data Payload Bandwidth at 30 MHz to 66 MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224

DS15BR400

Abstract: AN-1194 DS15BR400EVK DS15BR401 TQFP-48
Contextual Info: DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description Features The DS15BR400/DS15BR401 are four channel LVDS buffer/ repeaters capable of datarates of up to 2 Gbps. High speed data paths and flow-through pinout minimize internal device

Contextual Info: 19-2392; Rev 0; 4/02 LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver Features ♦ LVDS or LVTTL/LVCMOS Input Selection The MAX9160 is designed to operate with a 3.3V supply voltage over the extended temperature range of -40°C to +85°C. This device is available in 28-pin

DS15BR400

Abstract: AN-1194 DS15BR400EVK DS15BR401 TQFP-48
Contextual Info: DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description Features The DS15BR400/DS15BR401 are four channel LVDS buffer/ repeaters capable of datarates of up to 2 Gbps. High speed data paths and flow-through pinout minimize internal device

Contextual Info: ZL40220 Precision 2:6 LVDS Fanout Buffer with Glitch-free Input Reference Switching Data Sheet November 2012 Features Ordering Information ZL40220LDG1 32 Pin QFN Trays ZL40220LDF1 32 Pin QFN Tape and Reel Inputs/Outputs • Accepts two differential or single-ended inputs

MO-150

Abstract: SN65LV1023 SN65LV1023DB SN65LV1224 SN65LV1224DB SN65LVDS1023 SN65LVDS1224
Contextual Info: SN65LV1023/SN65LV1224 30ĆMHz TO 66ĆMHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005 D 300-Mbps to 660-Mbps Serial LVDS Data D D D Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

MAX9378

Abstract: MAX9377 MAX9377EUA MAX9378EUA
Contextual Info: 19-2846; Rev 1; 7/03 Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four Features ♦ Guaranteed 2GHz Switching Frequency ♦ Accept LVDS/LVPECL/Anything Inputs ♦ Pin-Selectable Divide-by-Four Function ♦ 421ps typ Propagation Delays (MAX9377)

Contextual Info: 19-2846; Rev 1; 7/03 Anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four The MAX9377/MAX9378 accept any differential input signal within the supply rails and with minimum amplitude of 100mV. Inputs are fully compatible with the LVDS, LVPECL, HSTL, and CML differential signaling

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Contextual Info: SN65LV1023/SN65LV1224 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527E – FEBRUARY 2002 – REVISED SEPTEMBER 2002 D D D D 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM

Contextual Info: V386 8-BIT LVDS RECEIVER FOR VIDEO General Description Features The V386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.38 Gbps throughput or 297.5 Mbytes per second. • Packaged in a 56-pin TSSOP Pb free available

Contextual Info: ZL40220 Precision 2:6 LVDS Fanout Buffer with Glitch-free Input Reference Switching Data Sheet February 2013 Features Ordering Information ZL40220LDG1 32 Pin QFN Trays ZL40220LDF1 32 Pin QFN Tape and Reel Inputs/Outputs • Accepts two differential or single-ended inputs

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Abstract: yx 805 YX 805 4 pin C 3686 ad9550 MO-220-WHHD GPON 77.76 FRAME GR-253-CORE JESD51-2 CP2121
Contextual Info: Integer-N Clock Translator for Wireline Communications AD9550 FEATURES BASIC BLOCK DIAGRAM REF PLL OUTPUT CIRCUITRY OUT2 OUT1 PIN DECODER AD9550 09057-001 Converts preset standard input frequencies to standard output frequencies Input frequencies from 8 kHz to 200 MHz

Contextual Info: SN65LV1023/SN65LV1224 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527D – FEBRUARY 2002 – REVISED AUGUST 2002 D D D D 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224

Contextual Info: SN65LV1023/SN65LV1224 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527D – FEBRUARY 2002 – REVISED AUGUST 2002 D D D D 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224

Contextual Info: Integer-N Clock Translator for Wireline Communications AD9550 FEATURES BASIC BLOCK DIAGRAM REF PLL OUTPUT CIRCUITRY OUT2 OUT1 PIN DECODER AD9550 09057-001 Converts preset standard input frequencies to standard output frequencies Input frequencies from 8 kHz to 200 MHz

MAX9110

Abstract: MAX9112 MAX9159 MAX9159ESA SN65LVDS9637 "DUAL LVDS"
Contextual Info: 19-2274; Rev 0; 1/02 Dual LVDS Line Receiver Features ♦ Pin Compatible with SN65LVDS9637 ♦ Fail-Safe Circuit Sets Output High for Undriven Inputs ♦ Conforms to ANSI TIA/EIA-644 Standard ♦ Single 3.3V Supply ♦ Designed for Data Rates up to 400Mbps