LVCMOS18 Search Results

4032V

Abstract: DS1017 LC4032V-10TN48I 4512c application LC4256V-75TN176C marking 17Z 4000B AEC-Q100 DS1020 22z2
Contextual Info: ispMACH 4000V/B/C/Z Family 3.3V/2.5V/1.8V In-System Programmable SuperFAST TM High Density PLDs Coolest Power May 2009 C Features Data Sheet DS1020 TM • Broad Device Offering • Multiple temperature range support – Commercial: 0 to 90°C junction Tj

XC3S700A

Abstract: xc3s200aft256 XC3S400AFT256 XC3S50A L01P L02P FG320 UG331 L05P xc3s400a ftg256
Contextual Info: Spartan-3A FPGA Family: Data Sheet R DS529 July 10, 2007 Product Specification Module 1: Introduction and Ordering Information - DS529-1 v1.4.1 July 10, 2007 • • • • • • • Introduction Features Architectural and Configuration Overview General I/O Capabilities

MachXO sysIO Usage Guide

Abstract: LCMXO256C-4M100C LCMXO2280 lcmxo640c-3tn100i LCMXO640C-3FT256C LCMXO1200 LCMXO256 LCMXO2280E-4M132I LVCMOS15 LVCMOS25
Contextual Info: MachXO Family Data Sheet Version 02.3_4W February 2007 MachXO Family Data Sheet Introduction April 2006 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL

Contextual Info: iCE40 LP/HX Family Data Sheet DS1040 Version 02.9, April 2014 iCE40 LP/HX Family Data Sheet Introduction February 2014 Data Sheet DS1040 Features  Flexible Logic Architecture – Schmitt trigger inputs, to 200 mV typical hysteresis • Programmable pull-up mode

Contextual Info: Artix-7 FPGAs Data Sheet: DC and Switching Characteristics DS181 v1.6 April 17, 2013 Product Specification Introduction Artix -7 FPGAs are available in -3, -2, -1, and -2L speed grades, with -3 having the highest performance. The -2L devices can operate at either of two VCCINT voltages, 0.9V

Contextual Info: Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics DS183 v1.18 November 26, 2013 Product Specification Introduction Virtex -7 T and XT FPGAs are available in -3, -2, -1, and -2L speed grades, with -3 having the highest performance.

UG628

Contextual Info: Spartan-6 FPGA Configuration User Guide UG380 v2.5 January 23, 2013 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL

020000040000FA

Abstract: AT17LV AT17LV002 AT17LV010 AT17LV512 CY3LV010 CY3LV512 CYDH2200E Cypress CY39100V208B processor RECONFIG
Contextual Info: Configuring Delta39K /Quantum38K™ CPLDs Overview This application note discusses the configuration interfaces, modes, and processes of the Delta39K™ and Quantum38K™ CPLDs and includes examples of device set-up. Each member of the Delta39K family is available in volatile

4032 k14

Abstract: 4512c PX6A10 4256b L5591 a/4032 k14 am 4512C LC45 4064C m6 pt80
Contextual Info: TM ispMACH 4000B/C Family 2.5V/1.8V In-System Programmable SuperFAST TM High Density PLDs December 2001 Data Sheet • Broad Device Offering Features • • • • ■ High Performance • fMAX = 350MHz maximum operating frequency • tPD = 2.5ns propagation delay

lfxp2-40e

Abstract: LVCMOS25 LD48 LFXP2-17E-5FTN256C HB1004 ispLEVER project Navigator route place LFXP2-5E-5QN IPUG35 LFXP2-8E
Contextual Info: LatticeXP2 Family Handbook HB1004 Version 02.9, May 2011 LatticeXP2 Family Handbook Table of Contents May 2011 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1

XAPP393

Abstract: DS090 VQ100 XC2C128 XC2C256 XC2C32 XC2C384 XC2C64 interfacing 8051 XC9500 cpld pins table
Contextual Info: R CoolRunner-II CPLD Family DS090 v1.7 October 2, 2003 Preliminary Product Specification Features • • • • Optimized for 1.8V systems - Industry’s fastest low power CPLD - Static Icc of less than 100 microamps at all times - Densities from 32 to 512 macrocells

SPARTAN-3 XC3S400 PQ208

Abstract: SPARTAN-3 XC3S400 pq208 architecture SPARTAN-3 XC3S400 tq144 SPARTAN-3 XC3S400 Spartan-3 FPGA Family XC3S4000-FG676 SPARTAN-3 XC3S400 pin SPARTAN-3 XC3S400 architecture XC3S4000FG676 XILINX SPARTAN VQG100
Contextual Info: 06 Spartan-3 FPGA Family: Introduction and Ordering Information R DS099-1 v1.4 January 17, 2005 Preliminary Product Specification Introduction - The Spartan -3 family of Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume,

XQ5VLX110

Abstract: XQ5VLX330T SX95T DS714 XQ5VFX130T ROCKETIO VIRTEX-5 LX110 UG190 UG191 UG195
Contextual Info: 74 Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics DS714 v2.0 December 17, 2009 Product Specification Virtex-5Q FPGA Electrical Characteristics Virtex -5Q FPGAs are available in -2 and -1 speed grades, with -2 having the highest performance. Virtex-5Q FPGA

XQ4VSX55

Abstract: xq4vlx25 XQ4VLX60-10FF668M XQ4VLX40 XQ4VFX60 xq4vlx60 XQ4VFX60-10EF672M XQ4VLX40-10FF668M XQ4VLX100 Virtex 4Q
Contextual Info: Virtex-4Q FPGA Data Sheet: DC and Switching Characteristics R DS595 v1.6 April 27, 2010 Product Specification Virtex-4Q FPGA Electrical Characteristics Defense-grade Virtex -4Q FPGAs are available in -10 speed grade and are qualified for industrial (TJ = –40°C to +100°C),

COOLRUNNER-II examples

Abstract: XA CoolRunner-II XAPP393 VQG44 CoolRunner-II CPLD AEC-Q100 TS16949 XA2C128 XA2C256 XA2C32A
Contextual Info: CoolRunner-II CPLD XA Product Family R DS315-1 v1.0 October 18, 2004 Advance Product Specification Features • • • • • AEC-Q100 device qualification and full PPAP support available in both extended temperature Q-grade and I-grade. Optimized for 1.8V systems

XC3S700AN FGG484

Abstract: XC3S400AN-FGG400 XC3S700A FGG484 xc3s200an XC3S400AN FGG400 FGG676 SPARTAN 3an XC3S50A XC3S700AN-FG484 XC3S700AN
Contextual Info: Spartan-3AN FPGA Family Data Sheet R DS557 June 2, 2008 Module 1: Introduction and Ordering Information - DS557-1 v3.1 June 2, 2008 • • • • • • • • Introduction Features Architectural Overview Configuration Overview In-system Flash Memory Overview

LVDSEXT-25

Abstract: 16x1D LVPECL33 16X1S LVDS-25 LVDS-33 LVDSEXT25 LVDCI18 LVDCI25 LVDS25
Contextual Info: Virtex-II 1.5V Field-Programmable Gate Arrays R DS031-2 v1.9 November 29, 2001 Advance Product Specification Detailed Description Input/Output Blocks (IOBs) Table 1: Supported Single-Ended I/O Standards Virtex-II I/O blocks (IOBs) are provided in groups of two or

UG366

Abstract: LX760
Contextual Info: Virtex-6 FPGA Data Sheet: DC and Switching Characteristics DS152 v3.5 May 17, 2013 Product Specification Virtex-6 FPGA Electrical Characteristics Virtex -6 FPGAs are available in -3, -2, -1, and -1L speed grades, with -3 having the highest performance. Virtex-6 FPGA

LCMXO2-1200HC-4TG100C

Abstract: LCMXO2-256HC-4TG100I LCMXO2-1200 tn1200 lcmxo2 LCMXO2-1200HC-4TG100 LCMXO2-2000 LCMXO2-7000 MachXO2-1200 LCMXO2-4000HC
Contextual Info: MachXO2 Family Handbook HB1010 Version 01.0, November 2010 MachXO2 Family Handbook Table of Contents November 2010 Section I. MachXO2 Family Data Sheet Introduction Features . 1-1

TPE11

Abstract: TPT20 CON6A v2 tpr4 pr48b PT13B condor E5 Condor LVCMOS15 LVCMOS25
Contextual Info: LatticeEC Standard Evaluation Board – Revision B User’s Guide April 2007 ebug10_01.4 Lattice Semiconductor LatticeEC Standard Evaluation Board – Revision B User’s Guide Introduction The LatticeEC Standard Evaluation Board provides a convenient platform to evaluate, test and debug user

LVCMOS25

Abstract: LVCMOS15 LVCMOS33 LVCMOS18 ECP2M date sheet of ninth class
Contextual Info: LatticeECP2/M sysIO Usage Guide June 2010 Technical Note TN1102 Introduction The LatticeECP2 and LatticeECP2M™ sysIO™ buffers give the designer the ability to easily interface with other devices using advanced system I/O standards. This technical note describes the sysIO standards available and

TN1178

Abstract: DDR3 DIMM footprint LVCMOS15 LVCMOS25 LVCMOS33 SSTL15D k2xsc
Contextual Info: LatticeECP3 High-Speed I/O Interface June 2010 Technical Note TN1180 Introduction LatticeECP3 devices support high-speed I/O interfaces, including Double Data Rate DDR and Single Data Rate (SDR) interfaces, using the logic built into the Programmable I/O (PIO). SDR applications capture data on one

smd 100uf Cha

Abstract: 5304 smd 8 pin ISPPAC-CLK5308S-01TN48I MBR120VLSFT1G RC0805JR-0710KL 100uF CHA ECS-3953M ic 5304 smd 8 pin SMD 100 6n cap DS1010
Contextual Info: ispClock Family Handbook HB1006 Version 01.4, November 2009 ispClock Family Handbook Table of Contents November 2009 Handbook HB1006 Section I. ispClock Family Data Sheets ispClock5600A Family Data Sheet. 1-1

OSC4/SM

Abstract: MDLS-20265 OPTREX C-51505 MDLS-24265 short stop 12v p18 30a rs232 converter dmx Mosfet J49 LCM-S01602 lcm-s02402 Vishay SOT23 MARKING F5
Contextual Info: LatticeXP2 Advanced Evaluation Board User’s Guide January 2009 Revision: EB30_01.3 LatticeXP2 Advanced Evaluation Board User’s Guide Lattice Semiconductor Introduction The LatticeXP2 Advanced Evaluation Board provides a convenient platform to evaluate, test and debug user