LVCH16601 Search Results

Contextual Info: 3.3V C M O S 18- BI T U N I V E R S A L BUS TRANSCEIVER WI TH 5 V O L T T O L E R A N T I/O Integra ted D evice Technology, inc. flip-flops to allow data flow in transparent, latched and clocked modes. Data flow in each direction is controlled by output-enable

IDT74LVCH16601A

Abstract: LVCH16601A SO56-2
Contextual Info: LVCH16601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT LVCH16601A UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD FEATURES: Data flow in each direction is controlled by output-enable OEAB and

74LVC05

Abstract: 7400 datasheet 2-input nand gate 74LVC05A LVC1G04 transistor x1 pv 25 inverter board design pv 74ALVC1G04 74ALVCH244 7400 nand gate series 74ALVC1G14
Contextual Info: Selector Guide for ALVC/LVC Products the leading provider of high-performance logic. From single-gate to 32-bit, IDT is your source for ALVC/LVC logic. Today’s designers are developing the most challenging telecommunications, networking and PC products ever designed

LVCH16601A

Contextual Info: LVCH16601A ADVANCE INFORMATION Q QUALITY SEMICONDUCTOR, INC. High-Speed CMOS 3.3V 18-Bit Registered Transceivers with Clock Enable and Bus Hold LVCH16601A ADVANCE INFORMATION FEATURES/BENEFITS DESCRIPTION • 5V tolerant inputs and outputs • Bus Hold feature holds last active state during

Contextual Info: 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD ID T 7 4 L V C H 1 6 6 0 1 A FE A T U R E S : - Typical tsK o Data flow in each direction is controlled by output-enable (OEAB and (Output Skew) < 250ps OEBA), latched-enable (LEAB and LEBA), and clock (CLKA B a n d C L K BA)

Contextual Info: LVCH16601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT LVCH16601A UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD FEATURES: DESCRIPTION: • Typical tSK o (Output Skew) < 250ps

IDT74LVCH16601A

Abstract: LVCH16601A
Contextual Info: LVCH16601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT LVCH16601A UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD FEATURES: DESCRIPTION: • Typical tSK o (Output Skew) < 250ps

Contextual Info: LVCH16601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT LVCH16601A UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD FEATURES: DESCRIPTION: • Typical tSK o (Output Skew) < 250ps

Contextual Info: LVCH16601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: - Data flow in each direction is controlled by output-enable OEAB and OEBA , latched-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled

ci 4074

Abstract: ic 4074 U 4074 B IDT74LVCH16601A LVCH16601A SO56-2 4074 750Vc
Contextual Info: 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 5 VOLT TOLERANT I/O Integrated Device Technology, Inc. FEATURES: LVCH16601A ADVANCE INFORMATION flip-flops to allow data flow in transparent, latched and clocked modes. Data flow in each direction is controlled by output-enable

ci 4074

Contextual Info: LVCH16601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD Data flow in each direction is controlled by output-enable OEAB and OEBA , latched-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled

ci 4074

Contextual Info: LVCH16601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT LVCH16601A UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD FEATURES: DESCRIPTION: • Typical tSK o (Output Skew) < 250ps

Contextual Info: TS\ s iconductor, inc . High-Speed CM063.3V 18- Bi t Regi stered Transcei vers with Q ock&able and Bus Hold q s 74l v c h i 66o ia advance in f o r m a t io n FEATURES/BENEFITS DESCRIPTION • 5V tolerant inputs and outputs • Bus Hold feature holds last active state during

Contextual Info: Q Semk» nductor, I nc. High-Speed CMOS 3.3V 18-Bit Registered Transceivers W ' th C l0 C k E n a b le a n d B u S H ° l d qs74lvchi66oia advance IN F 0 R M A T I0 N FEATURES/BENEFITS DESCRIPTION • 5V tolerant inputs and outputs • Bus Hold feature holds last active state during

Contextual Info: LVCH16601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT LVCH16601A UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD FEATURES: DESCRIPTION: • Typical tSK o (Output Skew) < 250ps

IDT74LVCH16601A

Abstract: LVCH16601A
Contextual Info: LVCH16601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT LVCH16601A UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD FEATURES: DESCRIPTION: • Typical tSK o (Output Skew) < 250ps