LVCH16501A Search Results
LVCH16501A Price and Stock
Integrated Device Technology Inc 74LVCH16501APABus XCVR Single 18-CH 3-ST 56-Pin TSSOP Tube |
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74LVCH16501APA | 138 |
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LVCH16501A Datasheets Context Search
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28C56Contextual Info: Q u a l it y S e m ic o n d u c t o r , I n c . High-Speed CMOS 3.3V 18-Bit Registered Transceivers with Bus Hold LVCH16501A ADVANCE INFORMATION FEATURES/BENEFITS DESCRIPTION • 5V tolerant inputs and outputs • Bus Hold feature holds last active state during |
OCR Scan |
18-bitqs74lvch16501a500mamdsl-00328-00+2 | |
74LVC05
Abstract: 7400 datasheet 2-input nand gate 74LVC05A LVC1G04 transistor x1 pv 25 inverter board design pv 74ALVC1G04 74ALVCH244 7400 nand gate series 74ALVC1G14
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32-bitcompatibilit-785074lvc057400 datasheet 2-input nand gate+8 | |
IDT74LVCH16501A
Abstract: LVCH16501A
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idt74lvch16501a18-bit250psmil-std-883+2 | |
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Contextual Info: 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD FE A T U R E S : - Typical - ESD > 2000V per MIL-STD-883, Method 3015; tsK o (Output Skew) < 250ps > 200V using machine model (C = 200pF, R = 0) - 0.635mm pitch SSOP, 0.50mm pitch TSSOP |
OCR Scan |
18-bitmil-std-883250ps200pf+3 | |
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Contextual Info: FS1 H ig h -S p e e d C M C 6 3 . 3 V 1 8 - B it R e g is t e r e d S E M ic Iu c ro R jN c T r a n s c e iv e r s w it h B u s H o ld q s 7 4 lv c h i6 5 o ia advance in f o r m a t io n FEATURES/BENEFITS DESCRIPTION • 5V tolerant inputs and outputs • Bus Hold feature holds last active state during |
OCR Scan |
mdsl-00328-00qs74lvch16501aqs74lvc18-bit | |
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Contextual Info: 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT TOLERANT I/O LVCH16501A IDT74LVCH162501A IDT74LVC16501A ADVANCE INFORMATION FEATURES: DESCRIPTION: • Common features: These 18-bit registered transceivers are built using ad vanced dual metal CMOS technology. These high-speed, low |
OCR Scan |
18-bitidt74lvch16501aidt74lvch162501aidt74lvc16501a+3 | |
LVCH16501AContextual Info: LVCH16501A ADVANCE INFORMATION Q QUALITY SEMICONDUCTOR, INC. High-Speed CMOS 3.3V 18-Bit Registered Transceivers with Bus Hold LVCH16501A ADVANCE INFORMATION FEATURES/BENEFITS DESCRIPTION • 5V tolerant inputs and outputs • Bus Hold feature holds last active state during |
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qs74lvch16501a18-bit500mamdsl-00328-00+2 | |
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Contextual Info: 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: - bit registered bus transceiver combines D-type latches and Dtype flip-flops to allow data flow in transparent latched and clocked modes. Data flow in each direction is controlled by |
OCR Scan |
18-bit250psmil-std-883200pf+5 | |
EL B17Contextual Info: 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD D E S C R IP TIO N FE A T U R E S : - Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP |
OCR Scan |
18-bitidt74lvch16501a250psmil-std-883+6 | |
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Contextual Info: LVCH16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT I/O INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT LVCH16501A REGISTERED BUS TRANSCEIVER WITH 5V TOLERANT I/O AND BUS-HOLD FEATURES: DESCRIPTION: • Typical tSK o (Output Skew) < 250ps |
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idt74lvch16501a18-bit250psmil-std-883+1 | |
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Contextual Info: 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: - bit registered bus transceiver com bines D-type latches and Dtype flip-flops to allow d ata flow in transparent latched and clocked m odes. Data flow in each direction is controlled by |
OCR Scan |
18-bitdt74lvch16501a | |
IDT74LVCH16501A
Abstract: LVCH16501A ma3688
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18-bitidt74lvch16501a250psmil-std-883+5 | |
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Contextual Info: LVCH16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT I/O INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT LVCH16501A REGISTERED BUS TRANSCEIVER WITH 5V TOLERANT I/O AND BUS-HOLD FEATURES: DESCRIPTION: • Typical tSK o (Output Skew) < 250ps |
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idt74lvch16501a18-bit250psmil-std-883+1 | |
SO56-2
Abstract: IDT74LVCH16501A LVCH16501A
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idt74lvch16501a18-bit250psmil-std-883+5 | |
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