LVCH1637 Search Results

Contextual Info: 3.3V C M O S 16-BIT R E G IS T E R 3-STATE WITH BUS HO LD AND 5 VOLT T O L E R A N T I/O IDT74LVCH1 6374A ADVANCE INFORMATION FE ATURES: DESCRIPTION: • C o m m o n feat ures: The LVCH16374A 16-bit edge-triggered D-type registers are built using advanced dual metal CMOS technology. These

Contextual Info: LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - The LVCH16373A 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. This high­ speed, low-power latch is ideal for tem porary storage of

Contextual Info: Integra ted D evice Technology, inc. 3.3V C M O S 16-BIT T R A N S P A R E N T LATCH WITH BUS HO LD AND 5 VOLT T O L E R A N T I/O IDT74LVCH1 6373A ADVANCE INFORMATION FE ATURES: DESCRIPTION: • C o m m o n feat ures: The LVCH16373A16-bit transparent D-type latches are built

lvch16373a

Contextual Info: LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - The LVCH16373A 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. This high­ speed, low-power latch is ideal for tem porary storage of

Contextual Info: LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT LVCH16374A EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, 5V TOLERANT I/O AND BUS-HOLD DESCRIPTION FEATURES: The LVCH16374A 16-bit edge-triggered D-type register is built using

IDT74LVCH16374A

Abstract: LVCH16374A
Contextual Info: LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT LVCH16374A EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, 5V TOLERANT I/O AND BUS-HOLD DESCRIPTION FEATURES: The LVCH16374A 16-bit edge-triggered D-type register is built using

IDT74LVCH16373A

Abstract: LVCH16373A
Contextual Info: LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION FEATURES: The LVCH16373A 16-bit transparent D-type latch is built using advanced

Contextual Info: LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION FEATURES: The LVCH16373A 16-bit transparent D-type latch is built using advanced

74LVC16373A

Abstract: 74LVC16373ADGG 74LVC16373ADL 74LVCH16373A 74LVCH16373ADGG 74LVCH16373ADL TSSOP48
Contextual Info: INTEGRATED CIRCUITS DATA SHEET 74LVC16373A; LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Product specification Supersedes data of 2002 Oct 02 2003 Dec 08 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V

SN74ALVCH16374

Contextual Info: LVCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES021 -JU L Y 1995 DGG OR DL PACKAGE {TOP VIEW Member of the Texas Instruments Widebus Family EPIC™ Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per

Contextual Info: 3.3V CMOS 16-BIT LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: - Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP

IDT74LVCH16373A

Abstract: LVCH16373A
Contextual Info: Integrated Device Technology, Inc. 3.3V CMOS 16-BIT TRANSPARENT LATCH WITH BUS HOLD AND 5 VOLT TOLERANT I/O LVCH16373A ADVANCE INFORMATION FEATURES: DESCRIPTION: • Common features: – Typical tSK o (Output Skew) < 250ps – ESD > 2000V per MIL-STD-883, Method 3015;

Contextual Info: LVCH16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS757A – DECEMBER 2003 – REVISED OCTOBER 2005 FEATURES • • • • • • • • • • • DGG, DGV, OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus

A115-A

Abstract: SN74LVCH16373A SN74LVCH16373ADL SN74LVCH16373AGRDR SN74LVCH16373AZRDR
Contextual Info: LVCH16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS568M – MARCH 1996 – REVISED FEBRUARY 2006 FEATURES • • • • • • • • DGG, DGV, OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Typical VOLP (Output Ground Bounce)

Contextual Info: LVCH16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS757A – DECEMBER 2003 – REVISED OCTOBER 2005 FEATURES • • • • • • • • • • • DGG, DGV, OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus

Contextual Info: LVCH16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS565K – MARCH 1996 – REVISED AUGUST 2002 D D D D D D D D D D D DGG, DGV, OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus  Family Operates From 1.65 V to 3.6 V

C101

Abstract: SN74LVCH16374A SN74LVCH16374ADL SN74LVCH16374AGRDR SN74LVCH16374AZRDR
Contextual Info: LVCH16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS757A – DECEMBER 2003 – REVISED OCTOBER 2005 FEATURES • • • • • • • • • • • DGG, DGV, OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus

C101

Abstract: SN74LVCH16374A SN74LVCH16374ADL SN74LVCH16374AGRDR SN74LVCH16374AZRDR
Contextual Info: LVCH16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS757A – DECEMBER 2003 – REVISED OCTOBER 2005 FEATURES • • • • • • • • • • • DGG, DGV, OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus

Contextual Info: LVCH16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS757A – DECEMBER 2003 – REVISED OCTOBER 2005 FEATURES • • • • • • • • • • • DGG, DGV, OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus

Contextual Info: LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: DESCRIPTION • Typical tSK o (Output Skew) < 250ps

Contextual Info: LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT LVCH16374A EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, 5V TOLERANT I/O AND BUS-HOLD FEATURES: DESCRIPTION • Typical tSK o (Output Skew) < 250ps

Contextual Info: LVCH16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS568M – MARCH 1996 – REVISED FEBRUARY 2006 FEATURES • • • • • • • • DGG, DGV, OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Typical VOLP (Output Ground Bounce)

smd 1le

Contextual Info: INTEGRATED CIRCUITS DATA SHEET 74LVC16373A; LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs 3-state Product specification Supersedes data of 1998 Mar 17 2002 Sep 12 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V

Contextual Info: LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT LVCH16374A EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, 5V TOLERANT I/O AND BUS-HOLD FEATURES: DESCRIPTION • Typical tSK o (Output Skew) < 250ps