LVC16543A Search Results

Contextual Info: LVC16543A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O D E S C R IP TIO N : FEATURES: - The LVC16543A16-bit registered transceiver is built using advanced dual metal CMOS technology. This high-speed, low-power device can

data link block diagram

Abstract: IDT74LVC16543A LVC16543A SO56-2
Contextual Info: LVC16543A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER EXTENDED COMMERCIAL TEMPERATURE RANGE LVC16543A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: The LVC16543A 16-bit registered transceiver is built using advanced

74LVC05

Abstract: 7400 datasheet 2-input nand gate 74LVC05A LVC1G04 transistor x1 pv 25 inverter board design pv 74ALVC1G04 74ALVCH244 7400 nand gate series 74ALVC1G14
Contextual Info: Selector Guide for ALVC/LVC Products the leading provider of high-performance logic. From single-gate to 32-bit, IDT is your source for ALVC/LVC logic. Today’s designers are developing the most challenging telecommunications, networking and PC products ever designed

Contextual Info: 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 5 VOLT TOLERANT I/O, 3-STATE OUTPUTS bit transceiver. Separate latch-enable LEAB or LEBA and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data

IDT74LVC16543A

Abstract: LVC16543A
Contextual Info: LVC16543A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE LVC16543A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O FEATURES: DESCRIPTION: • Typical tSK o (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

IDT74LVC16543A

Abstract: LVC16543A SO56-2 d1839
Contextual Info: LVC16543A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER EXTENDED COMMERCIAL TEMPERATURE RANGE LVC16543A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: Typical tSK 0 (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015;

Contextual Info: 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 5 VOLT TOLERANT I/O, 3-STATE OUTPUTS bit transceiver. S e p a ra te latch-enable LEAB or LEBA and output-enable (O E A B or O E B A ) inputs are provided for each register to permit independent control in either direction of data

d2136

Abstract: d1047 D2037
Contextual Info: 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O LVC16543A D E S C R IP TIO N : FEATURES: Typical - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-